Clarification required to do my Project

[Pandiarajan]

Hi everyone,
I am trying to implement a pattern matching algorithm for
Intrusion Detection system in FPGA's .The algorithm i ve developed has
lesser number of iterations compared to the existing algorithms. I ve
developed and tested it using "C"...But i get lot of errors while
compiling it in verilog.I ve listed down the problems im facing now.If
anyone knows the solution please reply asap.

-->How can i declare a string in verilog??
-->when i synthesize the verilog code in Xilinx i get a
error XST-1312 "Loop has iterated 64 times"...How can i correct the
error??
-->How can i view the timing report before and after
implementing in FPGA??
-->how to define a multi dimensional array??
-->how to reduce area and cost of FPGA by verilog
code??
-->what parameters can i show the simulated output??

with regards
AP

 

[glen herrmannsfeldt]

Pandiarajan <pandiarajan01@gmail.com> wrote:

I am trying to implement a pattern matching algorithm for
Intrusion Detection system in FPGA's .The algorithm i ve developed has
lesser number of iterations compared to the existing algorithms. I ve
developed and tested it using "C"...But i get lot of errors while
compiling it in verilog.I ve listed down the problems im facing now.If
anyone knows the solution please reply asap.

Without knowing which algorithm you are using, I always
recommend the systolic array architecture for pattern matching.

You might look into it, anyway.

Otherwise, C doesn't translate to verilog so well.

-- glen

 

[Pandiarajan]

On Feb 24, 7:14 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Pandiarajan <pandiaraja...@gmail.com> wrote:
       I am trying to implement a pattern matching algorithm for
Intrusion Detection system in FPGA's .The algorithm i ve developed has
lesser number of iterations compared to the existing algorithms. I ve
developed and tested it using "C"...But i get lot of errors while
compiling it in verilog.I ve listed down the problems im facing now.If
anyone knows the solution please reply asap.

Without knowing which algorithm you are using, I always
recommend the systolic array architecture for pattern matching.

You might look into it, anyway.

Otherwise, C doesn't translate to verilog so well.

-- glen

Thank yo Glen.i will go through it.
can yo explain how can i view the timing report before and after
implementing in FPGA ??

 

[mike]

I find that a standard editor works just dandy in opening the file.
Often is also d
isplayed with the tool that you are using to generate
it if you are using a GUI.

Viewing the report before its created is very difficult and I haven't
figured out how to do that.

Mike

can yo explain how can i view the timing report before and after
implementing in FPGA ??