CLA and half adder wave output problems

Guest
For some reason I am having problems with the output of this code for
the Carry-look-ahead and half adder. It took me some time to code it
and now I am having issues getting the correct wave outputs. Please
help me!! My test bench is include.
================================================================
//Verilog Code: 4-bit CLA adder (CLA.v)

module Add_half(sum, c_out, a, b);

input a, b;
output c_out, sum;

assign {cout,sum}= a + b;

endmodule

module cla4(c_output,c_in_0,g,p);

input c_in_0;
output [3:0] c_output; //declare 4-bit carry output
reg [3:0] c_output; //declare 4-bit carry output as reg for
always process
input [3:0] g; //declare 4-bit input (g)
input [3:0] p; //declare 4-bit input (p)

always @ (g or p) //start process, which starts soon as input
changes
begin
c_output[1] = g[0] + p[0]*c_in_0; //first equation,
c_output[2] = g[1] + p[1]* (g[0] + p[0]*c_in_0); //second
equation,
c_output[3] = g[2] + p[2]* (g[1] + p[1]* (g[0] +
p[0]*c_in_0) ); //third equation
end

endmodule


module TOP_MOD(a,b,s,in_bit);

input [3:0] a;
input [3:0] b;
input in_bit;
output [3:0] s; //final output values

wire [3:0] p;
wire [3:0] g;
wire [2:0] out_cla; //for the inputs of xor gates

Add_half U0 (.a(a[0]),.b(b[0]),.c_out(g[0]), .sum(p[0]));
Add_half U1 (.a(a[1]),.b(b[1]),.c_out(g[1]), .sum(p[1]));
Add_half U2 (.a(a[2]),.b(b[2]),.c_out(g[2]), .sum(p[2]));
Add_half U3 (.a(a[3]),.b(b[3]),.c_out(g[3]), .sum(p[3]));

cla4 U4(.c_output(out_cla), .c_in_0(in_bit), .g(g), .p(p));

assign s[0]= p[0]^in_bit;
assign s[1]= p[1]^out_cla[1];
assign s[2]= p[2]^out_cla[2];
assign s[3]= p[3]^out_cla[3];

endmodule
===============================================================
//Verilog Code: Testbench for CLA (CLA_tb.v)

module TB_CLA( );

parameter In_width_a = 4;
parameter In_width_b = 4;
parameter Out_width_s = 4;

reg[In_width_a-1:0]in_a_tb;
reg[In_width_b-1:0]in_b_tb;
reg c_in;
wire[Out_width_s-1:0]out_s_tb;

TOP_MOD U0(.a(in_a_tb),.b(in_b_tb),.s(out_s_tb),.in_bit(c_in));

initial
begin
in_a_tb = 4'b0000;
in_b_tb = 4'b0000;
c_in = 1'b0;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0011; in_b_tb = 4'b0010; c_in = 1'b1;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0111; in_b_tb = 4'b0000; c_in = 1'b1;
#50 in_a_tb = 4'b1111; in_b_tb = 4'b0001; c_in = 1'b0;
#50 in_a_tb = 4'b0101; in_b_tb = 4'b0010; c_in = 1'b1;
#50 $stop;
#20 $finish;
end


endmodule
================================================================
 
Tough homework assignment? Addition's taken care of by synthesis these
days, I thought, both in FPGA and ASIC realms.

So - rather than us doing your work for you - can you indicate where things
appear to start going wrong so we can help you troubleshoot your coding
troubles?


<uraniumore235@hotmail.com> wrote in message
news:1173389065.535713.18480@v33g2000cwv.googlegroups.com...
For some reason I am having problems with the output of this code for
the Carry-look-ahead and half adder. It took me some time to code it
and now I am having issues getting the correct wave outputs. Please
help me!! My test bench is include.
================================================================
//Verilog Code: 4-bit CLA adder (CLA.v)

module Add_half(sum, c_out, a, b);

input a, b;
output c_out, sum;

assign {cout,sum}= a + b;

endmodule

module cla4(c_output,c_in_0,g,p);

input c_in_0;
output [3:0] c_output; //declare 4-bit carry output
reg [3:0] c_output; //declare 4-bit carry output as reg for
always process
input [3:0] g; //declare 4-bit input (g)
input [3:0] p; //declare 4-bit input (p)

always @ (g or p) //start process, which starts soon as input
changes
begin
c_output[1] = g[0] + p[0]*c_in_0; //first equation,
c_output[2] = g[1] + p[1]* (g[0] + p[0]*c_in_0); //second
equation,
c_output[3] = g[2] + p[2]* (g[1] + p[1]* (g[0] +
p[0]*c_in_0) ); //third equation
end

endmodule


module TOP_MOD(a,b,s,in_bit);

input [3:0] a;
input [3:0] b;
input in_bit;
output [3:0] s; //final output values

wire [3:0] p;
wire [3:0] g;
wire [2:0] out_cla; //for the inputs of xor gates

Add_half U0 (.a(a[0]),.b(b[0]),.c_out(g[0]), .sum(p[0]));
Add_half U1 (.a(a[1]),.b(b[1]),.c_out(g[1]), .sum(p[1]));
Add_half U2 (.a(a[2]),.b(b[2]),.c_out(g[2]), .sum(p[2]));
Add_half U3 (.a(a[3]),.b(b[3]),.c_out(g[3]), .sum(p[3]));

cla4 U4(.c_output(out_cla), .c_in_0(in_bit), .g(g), .p(p));

assign s[0]= p[0]^in_bit;
assign s[1]= p[1]^out_cla[1];
assign s[2]= p[2]^out_cla[2];
assign s[3]= p[3]^out_cla[3];

endmodule
===============================================================
//Verilog Code: Testbench for CLA (CLA_tb.v)

module TB_CLA( );

parameter In_width_a = 4;
parameter In_width_b = 4;
parameter Out_width_s = 4;

reg[In_width_a-1:0]in_a_tb;
reg[In_width_b-1:0]in_b_tb;
reg c_in;
wire[Out_width_s-1:0]out_s_tb;

TOP_MOD U0(.a(in_a_tb),.b(in_b_tb),.s(out_s_tb),.in_bit(c_in));

initial
begin
in_a_tb = 4'b0000;
in_b_tb = 4'b0000;
c_in = 1'b0;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0011; in_b_tb = 4'b0010; c_in = 1'b1;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0111; in_b_tb = 4'b0000; c_in = 1'b1;
#50 in_a_tb = 4'b1111; in_b_tb = 4'b0001; c_in = 1'b0;
#50 in_a_tb = 4'b0101; in_b_tb = 4'b0010; c_in = 1'b1;
#50 $stop;
#20 $finish;
end


endmodule
================================================================
Click to expand...
 
I took the time to look through your code enough to realize your problem is
probably not with the logic, it's with Verilog.

You are using common boolean expressions to describe the carry look-ahead
structure, quite possible straight out of a text. (They still uses texts,
don't they?) What, for instance, would the text use for the XOR operator?
Wouldn't it be a circled plus sign? Where's that on the keyboard?

Verilog bitwise AND operation is the ampersand - & - and the bitwise OR
operator is the vertical line or pipe character - | - which are not to be
found in your cla module code.

What do you get when g, p, and c are all asserted in the equation g + p*c ?
If you look at your text and consider the math, you might find that you're
really implementing an XOR once the bits settle out. You want an OR
function, don't you?

- John_H


<uraniumore235@hotmail.com> wrote in message
news:1173389065.535713.18480@v33g2000cwv.googlegroups.com...
For some reason I am having problems with the output of this code for
the Carry-look-ahead and half adder. It took me some time to code it
and now I am having issues getting the correct wave outputs. Please
help me!! My test bench is include.
================================================================
//Verilog Code: 4-bit CLA adder (CLA.v)

module Add_half(sum, c_out, a, b);

input a, b;
output c_out, sum;

assign {cout,sum}= a + b;

endmodule

module cla4(c_output,c_in_0,g,p);

input c_in_0;
output [3:0] c_output; //declare 4-bit carry output
reg [3:0] c_output; //declare 4-bit carry output as reg for
always process
input [3:0] g; //declare 4-bit input (g)
input [3:0] p; //declare 4-bit input (p)

always @ (g or p) //start process, which starts soon as input
changes
begin
c_output[1] = g[0] + p[0]*c_in_0; //first equation,
c_output[2] = g[1] + p[1]* (g[0] + p[0]*c_in_0); //second
equation,
c_output[3] = g[2] + p[2]* (g[1] + p[1]* (g[0] +
p[0]*c_in_0) ); //third equation
end

endmodule


module TOP_MOD(a,b,s,in_bit);

input [3:0] a;
input [3:0] b;
input in_bit;
output [3:0] s; //final output values

wire [3:0] p;
wire [3:0] g;
wire [2:0] out_cla; //for the inputs of xor gates

Add_half U0 (.a(a[0]),.b(b[0]),.c_out(g[0]), .sum(p[0]));
Add_half U1 (.a(a[1]),.b(b[1]),.c_out(g[1]), .sum(p[1]));
Add_half U2 (.a(a[2]),.b(b[2]),.c_out(g[2]), .sum(p[2]));
Add_half U3 (.a(a[3]),.b(b[3]),.c_out(g[3]), .sum(p[3]));

cla4 U4(.c_output(out_cla), .c_in_0(in_bit), .g(g), .p(p));

assign s[0]= p[0]^in_bit;
assign s[1]= p[1]^out_cla[1];
assign s[2]= p[2]^out_cla[2];
assign s[3]= p[3]^out_cla[3];

endmodule
===============================================================
//Verilog Code: Testbench for CLA (CLA_tb.v)

module TB_CLA( );

parameter In_width_a = 4;
parameter In_width_b = 4;
parameter Out_width_s = 4;

reg[In_width_a-1:0]in_a_tb;
reg[In_width_b-1:0]in_b_tb;
reg c_in;
wire[Out_width_s-1:0]out_s_tb;

TOP_MOD U0(.a(in_a_tb),.b(in_b_tb),.s(out_s_tb),.in_bit(c_in));

initial
begin
in_a_tb = 4'b0000;
in_b_tb = 4'b0000;
c_in = 1'b0;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0011; in_b_tb = 4'b0010; c_in = 1'b1;
#50 in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50 in_a_tb = 4'b0111; in_b_tb = 4'b0000; c_in = 1'b1;
#50 in_a_tb = 4'b1111; in_b_tb = 4'b0001; c_in = 1'b0;
#50 in_a_tb = 4'b0101; in_b_tb = 4'b0010; c_in = 1'b1;
#50 $stop;
#20 $finish;
end


endmodule
================================================================
Click to expand...
 
On Thu, 8 Mar 2007 14:43:40 -0800, "John_H"
<newsgroup@johnhandwork.com> wrote:

I took the time to look through your code enough to realize your problem is
probably not with the logic, it's with Verilog.
Click to expand...
Not really; the problem is the syntax mismatch between the text &
verilog and the OP not noticing/knowing that "+" in the text means
"OR" not binary addition which as you say resolves to XOR for the LSB.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top