Choosing PLL

[ALuPin]

Hi,

I have the following problem:

The Altera Cyclone device I am using does have two PLLs.

Because of the fact that I am using only one PLL the compiler
seems to use PLL1 on bank 1 of the device.

But I need to route the external clock output of the PLL to bank 3 of
the device. For that purpose I need PLL2 at bank 3 to be used.

How can I tell the compiler not to use PLL1 (bank 1) but PLL2 (bank 3) ?
Is there some option?


I would be very thankful for your help.

Besr regards
André V.

 

[Subroto Datta]

ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407280514.48df66a9@posting.google.com>...

Hi,

I have the following problem:

The Altera Cyclone device I am using does have two PLLs.

Because of the fact that I am using only one PLL the compiler
seems to use PLL1 on bank 1 of the device.

But I need to route the external clock output of the PLL to bank 3 of
the device. For that purpose I need PLL2 at bank 3 to be used.

How can I tell the compiler not to use PLL1 (bank 1) but PLL2 (bank 3) ?
Is there some option?

The steps to do this are as follows, after you have compiled the
design once:

1. Open the Assignment Editor, using Tools->Assignment Editor.
2. Click on the Category drop down at the top of the Assignment Editor
to say PLL.
3. Double Click in an empty cell in the To column and then click on
the right arrow button to open the Node finder. Select the PLL name
that you created. (if you do not compile the design as specified in
Step1 you will not see the PLL name).
4. Click on the cell in the Location column and select PLL_2 from the
drop down.
5. Compile the design.

Alternatively if you prefer the command line type into the Quartus tcl
console:

set_location_assignment -to "foo:inst" PLL_2

where "foo:inst" is the instance that represents the PLL.

Hope this helps.
Subroto Datta
Altera Corp.