Chisel as alternative HDL

[Martin Schoeberl]

Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)

 

[garyr]

"Martin Schoeberl" <martin@jopdesign.com> wrote in message
news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...

Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)

You might find this interesting: http://www.myhdl.org

 

[Martin Schoeberl]

"garyr" <garyr@fidalgo.net> wrote:

"Martin Schoeberl" <martin@jopdesign.com> wrote in message
news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...
Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)


You might find this interesting: http://www.myhdl.org

Thanks for pointing this out, although it was not the 'real' answer to
my question ;-)

I'm already looking at MyHDL and some other projects. chisel just lookes
most promising at the moment. Maybe I change my mind.

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

Martin

 

[Jon Elson]

Martin Schoeberl wrote:

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

 

[Christopher Felton]

On 12/28/12 11:25 PM, Martin Schoeberl wrote:

"garyr" <garyr@fidalgo.net> wrote:
"Martin Schoeberl" <martin@jopdesign.com> wrote in message
news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...
Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)


You might find this interesting: http://www.myhdl.org

Thanks for pointing this out, although it was not the 'real' answer to
my question ;-)

I'm already looking at MyHDL and some other projects. chisel just lookes
most promising at the moment. Maybe I change my mind.

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

Martin

Typically to do a comparison you have to have an example/project fairly
limited in scope. It is hard to realize the benefits with such small
examples. A language might have a /nice/ description for example "A"
but is horrible at parametrization or it can be difficult to connect
many modules or fails miserably at example "B" and "C".

I am not familiar with Chisel and Scala and cannot comment directly. I
am familiar with MyHDL and I have used MyHDL successfully for commercial
and independent projects.

Regards,
Chris

 

[Martin Schoeberl]

Jon Elson <elson@pico-systems.com> wrote:

Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.

Martin

 

[Jon Elson]

Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!

Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon

 

[Christopher Felton]

On 12/30/12 4:42 PM, Jon Elson wrote:

Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon

You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

 

[Martin Schoeberl]

Christopher Felton <abc@def.org> wrote:

On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin

 

[Christopher Felton]

On 1/2/13 8:35 PM, Martin Schoeberl wrote:

Christopher Felton <abc@def.org> wrote:
On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin

I believe this is the original paper:
http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf

But note the objections in the previous thread I posted. The
comparisons are incomplete (comparing non-working HDL, the author(s)
didn't learn enough of the languages).

Regards,
Chris

 

[Martin Schoeberl]

Christopher Felton <abc@def.org> wrote:

On 1/2/13 8:35 PM, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin


I believe this is the original paper:
http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf

But note the objections in the previous thread I posted. The comparisons
are incomplete (comparing non-working HDL, the author(s) didn't learn
enough of the languages).

Regards,
Chris

Thanks for pointing me to the paper. It is not a very exciting one and I
agree on all critics. I did not look into all details, but I think the FIFO
example is also broken. There is only one pointer, but one would need a
read and a write pointer.

Untested code and no synthesis results. Ok, it is just a student
conference.

With this paper as reference it should be easy to do better ;-)

Cheers,
Martin

 

[David Brown]

On 03/01/13 23:50, Martin Schoeberl wrote:

Christopher Felton <abc@def.org> wrote:
On 1/2/13 8:35 PM, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin


I believe this is the original paper:
http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf

But note the objections in the previous thread I posted. The comparisons
are incomplete (comparing non-working HDL, the author(s) didn't learn
enough of the languages).

Regards,
Chris

Thanks for pointing me to the paper. It is not a very exciting one and I
agree on all critics. I did not look into all details, but I think the FIFO
example is also broken. There is only one pointer, but one would need a
read and a write pointer.

Untested code and no synthesis results. Ok, it is just a student
conference.

With this paper as reference it should be easy to do better ;-)

Cheers,
Martin

It is also worth noting that this "paper" seems to be just a student
exercise that has somehow "escaped" into public domain - it makes no
claims about trying to compare a realistic choice of languages. A HDL
language comparison that doesn't even include Verilog cannot be taken
seriously. I'm sure the student gave a good answer to the question his
teacher posed, but don't read more into it than that.

 

[Christopher Felton]

On 1/4/2013 2:56 AM, David Brown wrote:

On 03/01/13 23:50, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 1/2/13 8:35 PM, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin


I believe this is the original paper:
http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf

But note the objections in the previous thread I posted. The comparisons
are incomplete (comparing non-working HDL, the author(s) didn't learn
enough of the languages).

Regards,
Chris

Thanks for pointing me to the paper. It is not a very exciting one and I
agree on all critics. I did not look into all details, but I think the FIFO
example is also broken. There is only one pointer, but one would need a
read and a write pointer.

Untested code and no synthesis results. Ok, it is just a student
conference.

With this paper as reference it should be easy to do better ;-)

Cheers,
Martin


It is also worth noting that this "paper" seems to be just a student
exercise that has somehow "escaped" into public domain - it makes no
claims about trying to compare a realistic choice of languages. A HDL
language comparison that doesn't even include Verilog cannot be taken
seriously. I'm sure the student gave a good answer to the question his
teacher posed, but don't read more into it than that.

As you note, student paper escaped. But I do think
it would be reasonable to use only VHDL or Verilog
when comparing the plethora of alternative HDLs. I
believe the author was trying to explore non-traditional
HDLs (i.e. other than V*).

I don't think many would simply accept the conclusions but
it is a starting point for a conversation: how to compare
HDLs? How would one objectively quantify different HDLs.
What is being determined: speed of design entry, maintenance,
QoR, testabilty, ... ?

Regards,
Chris

 

[Paul Colin Gloster]

On 2013-01-04, David Brown <david@westcontrol.removethisbit.com>
sent:
|-----------------------------------------------------------------------|
|"[. . .] |
| |
|It is also worth noting that this "paper" seems to be just a student |
|exercise that has somehow "escaped" into public domain - it makes no |
|claims about trying to compare a realistic choice of languages. A HDL |
|language comparison that doesn't even include Verilog cannot be taken |
|seriously. I'm sure the student gave a good answer to the question his|
|teacher posed, but don't read more into it than that." |
|-----------------------------------------------------------------------|

Verilog is ignored in many publications produced by a lot of so-called
research in Europe.

Yours sincerely,
Colin Paul Gloster

 

[Nico Coesel]

Martin Schoeberl <martin@jopdesign.com> wrote:

"garyr" <garyr@fidalgo.net> wrote:
"Martin Schoeberl" <martin@jopdesign.com> wrote in message
news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...
Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)


You might find this interesting: http://www.myhdl.org

Thanks for pointing this out, although it was not the 'real' answer to
my question ;-)

I'm already looking at MyHDL and some other projects. chisel just lookes
most promising at the moment. Maybe I change my mind.

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

The problem with that approach is that you need to be proficient in
all the languages you try. Usually this isn't the case so language
comparisons are mostly useless. I'd stick to VHDL and learn how to use
it more efficiently. IMHO very few people are using the full potential
VHDL is offering. A lot of people still think in gates and counters
and produce netlists instead of an abstract description of what they
want to implement.

My prediction: The only HDL which will replace VDHL and Verilog has to
be based on a C style syntax. Look at C#, Java, PHP. All these
languages have gained a lot of popularity because it is based on what
people already know.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[Christopher Felton]

On 1/4/2013 9:19 AM, Nico Coesel wrote:

Martin Schoeberl <martin@jopdesign.com> wrote:

"garyr" <garyr@fidalgo.net> wrote:
"Martin Schoeberl" <martin@jopdesign.com> wrote in message
news:1621424063378432030.694310martin-jopdesign.com@reader.albasani.net...
Hi all,

started to look into alternatives to Verilog and VHDL and
stumbled over chisel from UCB:
http://chisel.eecs.berkeley.edu/

Any experiences and comment on this language?

Looks like some challenge for me as it involves practically
learning 3 new languages at once: chisel itself, Scala on which
it is based, and Verilog, which is produced (I'm used to VHDL).

Cheers,
Martin

PS: I was *very* long absent from this group ;-)


You might find this interesting: http://www.myhdl.org

Thanks for pointing this out, although it was not the 'real' answer to
my question ;-)

I'm already looking at MyHDL and some other projects. chisel just lookes
most promising at the moment. Maybe I change my mind.

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

The problem with that approach is that you need to be proficient in
all the languages you try. Usually this isn't the case so language
comparisons are mostly useless. I'd stick to VHDL and learn how to use
it more efficiently. IMHO very few people are using the full potential
VHDL is offering. A lot of people still think in gates and counters
and produce netlists instead of an abstract description of what they
want to implement.

My prediction: The only HDL which will replace VDHL and Verilog has to
be based on a C style syntax. Look at C#, Java, PHP. All these
languages have gained a lot of popularity because it is based on what
people already know.

I always struggle with the "C" HDL replacements. It seems like you are
going the wrong direction in abstraction and ease of use language.

But your argument is: There are many "C" programmers and/or folks that
feel comfortable with "C" style programming. If someone can create a
magical "C" like HDL language many will jump aboard ... hmmmmm

Regards,
Chris

 

[glen herrmannsfeldt]

Nico Coesel <nico@puntnl.niks> wrote:

Martin Schoeberl <martin@jopdesign.com> wrote:

(snip)

A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

The problem with that approach is that you need to be proficient in
all the languages you try. Usually this isn't the case so language
comparisons are mostly useless. I'd stick to VHDL and learn how to use
it more efficiently. IMHO very few people are using the full potential
VHDL is offering. A lot of people still think in gates and counters
and produce netlists instead of an abstract description of what they
want to implement.

My belief for some time has been that you have to think in terms of
gates and counters or you write lousy HDL code.

My prediction: The only HDL which will replace VDHL and Verilog has to
be based on a C style syntax. Look at C#, Java, PHP. All these
languages have gained a lot of popularity because it is based on what
people already know.

I suppose it depends somewhat on what type of designs you are working on.

For most of what I am interested in, making it look too much like C
might give people the idea that you could port a C algorithm without
any thought, but the algorithms that I am interested in are completely
different in systolic array hardware than in loops over arrays.

-- glen

 

[glen herrmannsfeldt]

Christopher Felton <nospam@nowhere.com> wrote:

(snip)

I always struggle with the "C" HDL replacements. It seems like you are
going the wrong direction in abstraction and ease of use language.

But your argument is: There are many "C" programmers and/or folks that
feel comfortable with "C" style programming. If someone can create a
magical "C" like HDL language many will jump aboard ... hmmmmm

Verilog isn't quite as C-like as I might think it could be.

I learned many years ago the difference between Pascal (semicolon
is a statement separator) and most other languages such as
PL/I and C (semicolon is a statement terminator).

Seems to me that verilog could have done its semicolon rules a
little differently to make it more obvious to C programmers.

-- glen

 

[Martin Schoeberl]

Christopher Felton <nospam@nowhere.com> wrote:

On 1/4/2013 2:56 AM, David Brown wrote:
On 03/01/13 23:50, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 1/2/13 8:35 PM, Martin Schoeberl wrote:
Christopher Felton <abc@def.org> wrote:
On 12/30/12 4:42 PM, Jon Elson wrote:
Martin Schoeberl wrote:

Jon Elson <elson@pico-systems.com> wrote:
Martin Schoeberl wrote:


A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language
and the efficiency of the resulting HW implementation.

MAN, that would be a landmark achievement! You might even go down
in history as the author of "the Schoeberl paper". Even if it wouldn't
change the (horrible) way I do designs now, it would sure be an
interesting read.

Jon

Maybe I should tone this done. Yes, it would be nice to have this example.
It would also be nice to have this comparison in a paper. Let's see where
this leads.

I will start on a smaller scale with simpler examples. Maybe up to a very
simple processor that I already have in VHDL. Will keep you informed along
the
path. If anybody would like to join this effort we can setup a repository.
Great, and thanks for putting in the effort!
Even a VERY simple example of the same function in several languages
could be quite instructive. But, a somewhat larger project would
be more likely to expose some of the deficiencies of this or that
language.

Jon


You might be interested in this rebuttal to a
paper that compared a couple non-traditional HDLs.

http://thread.gmane.org/gmane.comp.python.myhdl/2701

Regards,
Chris

This is definitely interesting, but the link is dead :-(

Do you have the title of that paper so I can try to Google it.

Cheers,
Martin


I believe this is the original paper:
http://referaat.cs.utwente.nl/conference/17/paper/7344/comparing-hardware-description-languages.pdf

But note the objections in the previous thread I posted. The comparisons
are incomplete (comparing non-working HDL, the author(s) didn't learn
enough of the languages).

Regards,
Chris

Thanks for pointing me to the paper. It is not a very exciting one and I
agree on all critics. I did not look into all details, but I think the FIFO
example is also broken. There is only one pointer, but one would need a
read and a write pointer.

Untested code and no synthesis results. Ok, it is just a student
conference.

With this paper as reference it should be easy to do better ;-)

Cheers,
Martin


It is also worth noting that this "paper" seems to be just a student
exercise that has somehow "escaped" into public domain - it makes no
claims about trying to compare a realistic choice of languages. A HDL
language comparison that doesn't even include Verilog cannot be taken
seriously. I'm sure the student gave a good answer to the question his
teacher posed, but don't read more into it than that.



As you note, student paper escaped. But I do think
it would be reasonable to use only VHDL or Verilog
when comparing the plethora of alternative HDLs. I
believe the author was trying to explore non-traditional
HDLs (i.e. other than V*).

I don't think many would simply accept the conclusions but
it is a starting point for a conversation: how to compare
HDLs? How would one objectively quantify different HDLs.
What is being determined: speed of design entry, maintenance,
QoR, testabilty, ... ?

Yes, this is not an easy question. However, this is also a reason
to attack this question. Maybe by some discussions here.

I personally want to explore alternatives ti VHDL and Verilog.
I think it is time for new languages, now. We still use V*, but
now as intermediate language to feed the design tools.

Cheers,
Martin

Regards,
Chris

 

[Nico Coesel]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

Nico Coesel <nico@puntnl.niks> wrote:
Martin Schoeberl <martin@jopdesign.com> wrote:

(snip)
A good comparison would be to do one HW design, e.g. a standard MIPS
pipeline, in all languages and compare the efficiency of the language and
the efficiency of the resulting HW implementation.

The problem with that approach is that you need to be proficient in
all the languages you try. Usually this isn't the case so language
comparisons are mostly useless. I'd stick to VHDL and learn how to use
it more efficiently. IMHO very few people are using the full potential
VHDL is offering. A lot of people still think in gates and counters
and produce netlists instead of an abstract description of what they
want to implement.

My belief for some time has been that you have to think in terms of
gates and counters or you write lousy HDL code.

That sounds like an assembly versus C discussion. In reality designs
get so big these days that hand optimising the last gate from a design
costs way more than using a bigger FPGA or ASIC. Besides that a high
level language usually offers a more structured approach which should
result in better maintainability, platform independance, re-usability,
etc. Just let the synthesizer deal with platform specifics and
optimisation.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
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