[Chip-Level synthesis] I/O synthesis constraints

Hi all,

What's the methodology for the chip-level synthesis?

I need to apply timing constraints to the Top level of the Chip [the
hierarchical level, which is next to the I/O's].

So, how should I do so? Actually I have all the constraints on the
I'O's [defined by SPEC]. So, how should I translate the constraints in
order to apply them on the Top level [the highest hierarchy just next
to the I/O ring hierarchy]?

Please help.