Chip IO Planning (how do you do it)?

[Poly Diffusion]

I'm a grad student with all the Cadence software.
How do folks in the industry do chip-level IO planning?

I (guess I) can trick Silicon Ensemble into doing IO placement.
I (guess I) can test the Cadence Chip IO planner.
I (guess I) can see if there is a Cadence Preview IO planner.
I (guess I) can dig up some working SKILL code for IO planning.
I (guess I) can use socencounter digital tools for IO planning.

My project has a non-functional chip of 10 million gates, half
of which are custom and half are digital. At the moment, I don't
even know how to approach basic IO cell and bond-pad placement,
let alone staggered (TSMC 'g' processes) or, heresy, flip chip.

Does everyone just read in a predetermined IO placement file?
Or does anyone actually optimize the chip-level IO cell placement?
If you do optimize the IO & bond-pad placement, what fundamental
approach is used in the industry?

Polly

 

[jools]

Im assuming you talking about placement of pins not pads and pins.

You can generate a io pin file in Silicon Ensemble and in SOC encounter,
which you can then edit or use as is. The documentation discusses this try
reading it from a detailed walk through. Bascially though PLACE>IO and the
in dialog select place from file. And if one doesnt exist when you click ok,
one will be generated for you with the name in the dialog. Dont be afraid to
press ok in the dialog as it doesnt actually try and place the pins if the
file doesnt exist it will just create it.

After creation you need to edit it as some pins may be in the ignore region.

"Poly Diffusion" <polydiff@yahoo.com> wrote in message
news:d22be724.0402250300.12cfc548@posting.google.com...

I'm a grad student with all the Cadence software.
How do folks in the industry do chip-level IO planning?

I (guess I) can trick Silicon Ensemble into doing IO placement.
I (guess I) can test the Cadence Chip IO planner.
I (guess I) can see if there is a Cadence Preview IO planner.
I (guess I) can dig up some working SKILL code for IO planning.
I (guess I) can use socencounter digital tools for IO planning.

My project has a non-functional chip of 10 million gates, half
of which are custom and half are digital. At the moment, I don't
even know how to approach basic IO cell and bond-pad placement,
let alone staggered (TSMC 'g' processes) or, heresy, flip chip.

Does everyone just read in a predetermined IO placement file?
Or does anyone actually optimize the chip-level IO cell placement?
If you do optimize the IO & bond-pad placement, what fundamental
approach is used in the industry?

Polly