Chip Assembly and Pad Assembly in ICC???

[Lee]

Dear all,

How to do verification after chip/pad assembly?Using circuit level
simulation for a big design is slow.

In Silicon Ensemble, I generated the clock tree for each block. After
chip/pad assembly, the design including all blocks is much bigger. How
can I deal with the global clock tree issue for whole design?

Thanks,

 

[Debbie Unger]

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0408090654.6413620d@posting.google.com>...

How to do verification after chip/pad assembly?Using circuit level
simulation for a big design is slow.

UltraSim