check it please

D

dolly

Guest
//module for a^n

module value1(v1_a,v1_out);
input v1_a;
output [15:0]v1_out;
assign v1_out = v1_a * v1_a * v1_a * v1_a;
endmodule


//module ( X2 = na^(n-1)b )
module value2(temp1, v2_a, v2_n, v2_b, v2_out);
input v2_a , v2_n , v2_b, temp1;
output [15:0] v2_out;
assign temp1 = v2_a * v2_a * v2_a ;
assign v2_out = v2_n * temp1 * v2_b;
endmodule

//module X3 ( X3 = n (n-1) a^(n-2) b^2 / 2 )
module value3(temp1,temp2, v3_a, v3_n, v3_b ,v3_out);
input v3_a , v3_n , v3_b, temp1, temp2;
output [15:0] v3_out;
assign temp1 = v3_n-1;
assign temp2 = v3_a * v3_a ;
assign v3_out = ( v3_n * temp1 * temp2 * v3_b * v3_b)/ 2;
endmodule

// module X4 ( X4 =n (n-1)(n-2) a^(n-3) b^3 / 6)
module value4(temp1,temp2,v4_a,v4_n,v4_b,v4_out);
input v4_a , v4_n , v4_b,temp1, temp2;
output [15:0] v4_out;
assign temp1 = v4_n - 1;
assign temp2 = v4_n - 2;
assign v4_out = (v4_n * temp1 * temp2 * v4_a * v4_b * v4_b * v4_b) /6;
endmodule

// for final result it do the addition
module answer (sum,r_final_out,r_ans1,r_ans2,r_ans3,r_ans4,c_in);
output [15:0]r_final_out;
input [15:0] r_ans1,r_ans2,r_ans3,r_ans4;
output sum;
input c_in;
wire sum, c_in;
wire[15:0] r_final_out, r_ans1,r_ans2,r_ans3,r_ans4;
value1 r1(.v1_out(r_ans1)) ;
value2 r2(.v2_out(r_ans2));
value3 r3(.v3_out(r_ans3));
value4 r4(.v4_out(r_ans4));
assign (sum , r_final_out) = r_ans1+ r_ans2 + r_ans3 + r_ans4 + c_in;

initial
$monitor("r_final_out=%d",r_final_out);

endmodule


// this is stimulus
module stimulus;
reg [15:0] a,n,b;
wire [15:0] ans1,ans2,ans3,ans4 ,final_out;


value1 v1(v1_a,ans1);
value2 v2(temp,a2,n2,b2,ans2);
value3 v3(tempa,tempb,a3,n3,b3,ans3);
value4 v4(tempc,tempd,a4,n4,b4,ans4);
answer r(add,c_i,ans1,ans2,ans3,ans4,final_out);


initial
begin
a= 10;
b= 10;
n= 4;

# 10;

a= 2;
b= 2;
n= 4;


# 10;

a=3;
b= 3;
n= 4;

# 10;

a= 4;
b= 4;
n= 4;
end
endmodule



i m getting error in module answer which says:
expecting STRENGTH0 or STRENGTH1 or SUPPLY0 or SUPPLY1.
at this point

assign (sum , r_final_out) = r_ans1+ r_ans2 + r_ans3 + r_ans4 + c_in;

i just simply want to add all the values and store the result in
r_final_out

i m not sure that my overall logic is correct or not ?

secondly i m hafing a gray area in timing diagram at r_final_out if i
simply do
assign r_final_out = r_ans1+ r_ans2 + r_ans3 + r_ans4;
(without c_in and sum)
please tell me why i m geting this error and how i solve it
 
Please find someone who can sit down with you to help point out your
troubles. Your attempts at Verilog code indicate you haven't bothered to
understand the sincere basics of the Verilog language. I'm guessing your
only (limited) experience has been with software.

DIMENSION YOUR VALUES. inputs, outputs, regs, wires... they should *all* be
dimensioned if they are larger than a 1-bit value. If you have an output
reg, BOTH dimensions for the output and for the reg must match. You do NOT
need to declare a new module for each and every piece of your equation.

I was tempted not to respond at all and let your plea for help fester but
instead choose to plea with YOU to find personal sit-down help with someone
else in or connected with your class. You won't find much sympathy on this
forum for information exchange when it comes to learning the utter basics of
verilog.

Good luck and farewell.


"dolly" <shehnaz.tariq@gmail.com> wrote in message
news:df34096458c92ac0d4b6e785e41ac561@localhost.talkaboutprogramming.com...
//module for a^n

module value1(v1_a,v1_out);
input v1_a;
output [15:0]v1_out;
assign v1_out = v1_a * v1_a * v1_a * v1_a;
endmodule


//module ( X2 = na^(n-1)b )
module value2(temp1, v2_a, v2_n, v2_b, v2_out);
input v2_a , v2_n , v2_b, temp1;
output [15:0] v2_out;
assign temp1 = v2_a * v2_a * v2_a ;
assign v2_out = v2_n * temp1 * v2_b;
endmodule

//module X3 ( X3 = n (n-1) a^(n-2) b^2 / 2 )
module value3(temp1,temp2, v3_a, v3_n, v3_b ,v3_out);
input v3_a , v3_n , v3_b, temp1, temp2;
output [15:0] v3_out;
assign temp1 = v3_n-1;
assign temp2 = v3_a * v3_a ;
assign v3_out = ( v3_n * temp1 * temp2 * v3_b * v3_b)/ 2;
endmodule

// module X4 ( X4 =n (n-1)(n-2) a^(n-3) b^3 / 6)
module value4(temp1,temp2,v4_a,v4_n,v4_b,v4_out);
input v4_a , v4_n , v4_b,temp1, temp2;
output [15:0] v4_out;
assign temp1 = v4_n - 1;
assign temp2 = v4_n - 2;
assign v4_out = (v4_n * temp1 * temp2 * v4_a * v4_b * v4_b * v4_b) /6;
endmodule

// for final result it do the addition
module answer (sum,r_final_out,r_ans1,r_ans2,r_ans3,r_ans4,c_in);
output [15:0]r_final_out;
input [15:0] r_ans1,r_ans2,r_ans3,r_ans4;
output sum;
input c_in;
wire sum, c_in;
wire[15:0] r_final_out, r_ans1,r_ans2,r_ans3,r_ans4;
value1 r1(.v1_out(r_ans1)) ;
value2 r2(.v2_out(r_ans2));
value3 r3(.v3_out(r_ans3));
value4 r4(.v4_out(r_ans4));
assign (sum , r_final_out) = r_ans1+ r_ans2 + r_ans3 + r_ans4 + c_in;

initial
$monitor("r_final_out=%d",r_final_out);

endmodule


// this is stimulus
module stimulus;
reg [15:0] a,n,b;
wire [15:0] ans1,ans2,ans3,ans4 ,final_out;


value1 v1(v1_a,ans1);
value2 v2(temp,a2,n2,b2,ans2);
value3 v3(tempa,tempb,a3,n3,b3,ans3);
value4 v4(tempc,tempd,a4,n4,b4,ans4);
answer r(add,c_i,ans1,ans2,ans3,ans4,final_out);


initial
begin
a= 10;
b= 10;
n= 4;

# 10;

a= 2;
b= 2;
n= 4;


# 10;

a=3;
b= 3;
n= 4;

# 10;

a= 4;
b= 4;
n= 4;
end
endmodule



i m getting error in module answer which says:
expecting STRENGTH0 or STRENGTH1 or SUPPLY0 or SUPPLY1.
at this point

assign (sum , r_final_out) = r_ans1+ r_ans2 + r_ans3 + r_ans4 + c_in;

i just simply want to add all the values and store the result in
r_final_out

i m not sure that my overall logic is correct or not ?

secondly i m hafing a gray area in timing diagram at r_final_out if i
simply do
assign r_final_out = r_ans1+ r_ans2 + r_ans3 + r_ans4;
(without c_in and sum)
please tell me why i m geting this error and how i solve it
Click to expand...
 
"dolly" <shehnaz.tariq@gmail.com> wrote in message news:<df34096458c92ac0d4b6e785e41ac561@localhost.talkaboutprogramming.com>...
//no need to repaste the rest.
Click to expand...

I highly suggest you take a look at some examples. As well I agree
with John that having someone sit by you and show you the ropes would
greatly help, altho I didnt have that luxary and so far Im getting the
hang of it based on what Ive found on the forum and as well some
differnt sites giving examples. Some good starter sites that have
helped me have been:

http://www.axonspace.com/start/ for getting started with the real
basics.
http://www.fpga4fun.com/ for a little more in depth look. has great
example projects.
http://www.deeps.org/verilog/index.html for basics as well as a good
reference.

theres plenty more out there as well, good luck to you!

-Mark
 
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