cheap Xilinx tricks

J

John Larkin

Guest
Hi,

Given a Spartan 3 chip, what I'd like to do is arrange two pins as an
LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable
driver drive one of those pins. From what I know of the output cell
architecture, it looks pretty likely that the hardware resources
exist. My guys are using ISE with schematic entry, and I'm not an ISE
driver, but they say it can't be done, or at least ISE won't let them
do it.

Any ideas? It would be very cool if this would work; it would save us
a bunch of pins and a bunch of picofarads.

Thanks,

John
 
"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
message news:bhq941lt94e85vk90uvgvh0472sm883csj@4ax.com...
Hi,

Given a Spartan 3 chip, what I'd like to do is arrange two pins as an
LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable
driver drive one of those pins. From what I know of the output cell
architecture, it looks pretty likely that the hardware resources
exist. My guys are using ISE with schematic entry, and I'm not an ISE
driver, but they say it can't be done, or at least ISE won't let them
do it.

Any ideas? It would be very cool if this would work; it would save us
a bunch of pins and a bunch of picofarads.

Thanks,

John
Click to expand...
John,

I can't imagine why you need to do something like this (LVDS diff input with
one pin (p or n) also being an LVTTL output?), but here are some ideas.

The first problem is that the LVDS for Spartan 3 is only defined for VCCO of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O) at
the same time. You could add a third IOB (in a separate 3.3V VCCO bank) and
connect it to one of your LVDS pins (in the 2.5V VCCO bank), but you'll have
to play some tricks to insure that you don't overdrive the input-to-supply
diode on the LVDS input (when the LVTTL output drives high). This trick
could be as simple as adding a series resistor between the LVTTL pin and the
LVDS pin -- to insure that the input diode never draws more than 10mA when
the 3.3V output is driving high.

Bob
 
If you add the I/O symbols like IBUFGDS_LVDS_25(clock input) or
IBUF_LVDS_25(normal input) to your schematic you will get a proper LVDS
input implementation. With Spartan-3 you will need an external terminating
resistor for input LVDS. For information on buffer types etc look in the
"libraries guide". You will need to dig for the LVDS in particular as text
searching this document does work well for finding a particular I/O standard
buffer type.

I think you can mix LVDS (input only and not DCI mode) with a 3.3V output
but either check that with your FAE or try in on a development board. I have
done this exactly on a Virtex2-Pro but personally have not tried this
combination on Spartan-3.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
message news:bhq941lt94e85vk90uvgvh0472sm883csj@4ax.com...
Hi,

Given a Spartan 3 chip, what I'd like to do is arrange two pins as an
LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable
driver drive one of those pins. From what I know of the output cell
architecture, it looks pretty likely that the hardware resources
exist. My guys are using ISE with schematic entry, and I'm not an ISE
driver, but they say it can't be done, or at least ISE won't let them
do it.

Any ideas? It would be very cool if this would work; it would save us
a bunch of pins and a bunch of picofarads.

Thanks,

John
Click to expand...
 
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

The first problem is that the LVDS for Spartan 3 is only defined for VCCO of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O) at
the same time.
Click to expand...
VCCO only supplies differential drivers the differential receivers run from
VCCAUX so I see no reason why you can't have LVDS receivers in a bank with
3.3v VCCO. I have done this without problem but so far only on a prototype.

For the OP I suggest you look at an IOB with the FPGA editor and see if you
can find a combination of checkboxes to give you what you want. I suspect
there isn't but if there is you will have to find out how to make the tools
give you what you want.
 
On Sat, 26 Mar 2005 08:45:26 -0000, "John Adair"
<removethisthenleavejea@replacewithcompanyname.co.uk> wrote:

If you add the I/O symbols like IBUFGDS_LVDS_25(clock input) or
IBUF_LVDS_25(normal input) to your schematic you will get a proper LVDS
input implementation. With Spartan-3 you will need an external terminating
resistor for input LVDS. For information on buffer types etc look in the
"libraries guide". You will need to dig for the LVDS in particular as text
searching this document does work well for finding a particular I/O standard
buffer type.

I think you can mix LVDS (input only and not DCI mode) with a 3.3V output
but either check that with your FAE or try in on a development board. I have
done this exactly on a Virtex2-Pro but personally have not tried this
combination on Spartan-3.
Click to expand...
What we want to do works fine electrically - we've tried it - but it
takes three pins. We have to externally connect the tristate output to
one of the LVDS inputs. What I want to do is persuade the ISE compiler
to make the connection internally so we can save a pin each time we do
this.

I think all the required hardware exists inside the S3 I/O cell. What
we can't do is get the ISE software to configure it that way. I'm
fishing for ideas on that.

Thanks,

John
 
"nospam" <nospam@nospam.invalid> wrote in message
news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com...
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

The first problem is that the LVDS for Spartan 3 is only defined for VCCO
of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O)
at
the same time.

VCCO only supplies differential drivers the differential receivers run
from
VCCAUX so I see no reason why you can't have LVDS receivers in a bank with
3.3v VCCO. I have done this without problem but so far only on a
prototype.

For the OP I suggest you look at an IOB with the FPGA editor and see if
you
can find a combination of checkboxes to give you what you want. I suspect
there isn't but if there is you will have to find out how to make the
tools
give you what you want.
Click to expand...
I think you're correct about the LVDS input diff amp running from VCCAUX.
However, since VCCAUX is 2.5V (for S3), I wonder if you could still
overdrive the 2.5V input stage by the 3.3V topside output fet. It may work,
but the long-term reliability may be in question.

I'd still like to know why John needs to mix LVDS and a single-ended output.
It's probably something evil or illegal ;-O

Bob
 
On Sat, 26 Mar 2005 17:04:30 GMT, "Bob"
<nimby1_notspamm_@earthlink.net> wrote:

"nospam" <nospam@nospam.invalid> wrote in message
news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com...
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

The first problem is that the LVDS for Spartan 3 is only defined for VCCO
of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O)
at
the same time.

VCCO only supplies differential drivers the differential receivers run
from
VCCAUX so I see no reason why you can't have LVDS receivers in a bank with
3.3v VCCO. I have done this without problem but so far only on a
prototype.

For the OP I suggest you look at an IOB with the FPGA editor and see if
you
can find a combination of checkboxes to give you what you want. I suspect
there isn't but if there is you will have to find out how to make the
tools
give you what you want.



I think you're correct about the LVDS input diff amp running from VCCAUX.
However, since VCCAUX is 2.5V (for S3), I wonder if you could still
overdrive the 2.5V input stage by the 3.3V topside output fet. It may work,
but the long-term reliability may be in question.
Click to expand...
As I said, we did it with an external connection, and it worked great.

Our only problem is the danged compiler. If you look at figure 1 of
the DS099-2.pdf thing, it sure looks like all the wires I want are
there. In fact, if we can take this diagram literally, the ttl
tristate driver is already connected to one pin of the LVDS receiver.

I'd still like to know why John needs to mix LVDS and a single-ended output.
It's probably something evil or illegal ;-O
Click to expand...
Both. It's so terrible that if I told you, The Authorities would take
away my slide rule.

John
 
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

I think you're correct about the LVDS input diff amp running from VCCAUX.
However, since VCCAUX is 2.5V (for S3), I wonder if you could still
overdrive the 2.5V input stage by the 3.3V topside output fet. It may work,
but the long-term reliability may be in question.
Click to expand...
I doubt it is a problem. If you look at the simplified IOB schematic all
receiver styles appear to be connected to the pin regardless of the pin
being configured as in or out with whatever standard. I can only assume all
receivers can take the worst a pin can output.

The pin clamp diode is connected to VCCO. The datasheet absolute maximum
input voltage ratings are specified in relation to VCCO only (apart from
dedicated pins which appear to run from VCCAUX).
 
John Larkin wrote:

I think all the required hardware exists inside the S3 I/O cell. What
we can't do is get the ISE software to configure it that way. I'm
fishing for ideas on that.
Click to expand...
I've done similar things in the past by:

Compiling the design.
Converting to XDL.
Edit the XDL with a script (Perl would be a good choice)
Build the design.

Type XDL at a command prompt.

"XDL is also a fully featured Physical Design language that
provides direct read and write access to Xilinx's proprietary
Native Circuit Description (NCD). This access enables all
users to write tools to address their individual FPGA
design needs."


Another method is to use FPGA_editor to create a hard macro, and put
this into your design. This probably requires two wrapper files, one
for simulation and one for synthesis.


--
Phil Hays
Phil-hays at posting domain (- .net + .com) should work for email
 
On Sat, 26 Mar 2005 10:45:58 -0800, John Larkin
<jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:

On Sat, 26 Mar 2005 17:04:30 GMT, "Bob"
nimby1_notspamm_@earthlink.net> wrote:


"nospam" <nospam@nospam.invalid> wrote in message
news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com...
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

The first problem is that the LVDS for Spartan 3 is only defined for VCCO
of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O)
at
the same time.

VCCO only supplies differential drivers the differential receivers run
from
VCCAUX so I see no reason why you can't have LVDS receivers in a bank with
3.3v VCCO. I have done this without problem but so far only on a
prototype.

For the OP I suggest you look at an IOB with the FPGA editor and see if
you
can find a combination of checkboxes to give you what you want. I suspect
there isn't but if there is you will have to find out how to make the
tools
give you what you want.



I think you're correct about the LVDS input diff amp running from VCCAUX.
However, since VCCAUX is 2.5V (for S3), I wonder if you could still
overdrive the 2.5V input stage by the 3.3V topside output fet. It may work,
but the long-term reliability may be in question.


As I said, we did it with an external connection, and it worked great.

Our only problem is the danged compiler. If you look at figure 1 of
the DS099-2.pdf thing, it sure looks like all the wires I want are
there. In fact, if we can take this diagram literally, the ttl
tristate driver is already connected to one pin of the LVDS receiver.

I'd still like to know why John needs to mix LVDS and a single-ended output.
It's probably something evil or illegal ;-O

Both. It's so terrible that if I told you, The Authorities would take
away my slide rule.

John
Click to expand...
As suggested by nospam, you might get what you want using the FPGA
editor. To minimize the amount of fudging, have your ISE schematic
entry person do this:

- Instantiate both pins as IOPAD
- Instantiate IBUFDS with IOSTANDARD=LVDS_25
- instantiate OBUFTDS with IOSTANDARD=LVDS_25
- wire the diff sides of the IBUFDS and OBUFTDS to the IOPADs
- wire the OBUFTDS inputs as if it is your desired OBUFT
- after compilation use FPGA editor to tweak the IOB to make the
output side an OBUFT. You can capture this as a macro for
repeatability and documentation purposes.

Let us know if this works.

================================

Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com
 
On Mon, 28 Mar 2005 21:52:51 -0500, Greg Neff <greg@nospam.com> wrote:

On Sat, 26 Mar 2005 10:45:58 -0800, John Larkin
jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:

On Sat, 26 Mar 2005 17:04:30 GMT, "Bob"
nimby1_notspamm_@earthlink.net> wrote:


"nospam" <nospam@nospam.invalid> wrote in message
news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com...
"Bob" <nimby1_notspamm_@earthlink.net> wrote:

The first problem is that the LVDS for Spartan 3 is only defined for VCCO
of
2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O)
at
the same time.

VCCO only supplies differential drivers the differential receivers run
from
VCCAUX so I see no reason why you can't have LVDS receivers in a bank with
3.3v VCCO. I have done this without problem but so far only on a
prototype.

For the OP I suggest you look at an IOB with the FPGA editor and see if
you
can find a combination of checkboxes to give you what you want. I suspect
there isn't but if there is you will have to find out how to make the
tools
give you what you want.



I think you're correct about the LVDS input diff amp running from VCCAUX.
However, since VCCAUX is 2.5V (for S3), I wonder if you could still
overdrive the 2.5V input stage by the 3.3V topside output fet. It may work,
but the long-term reliability may be in question.


As I said, we did it with an external connection, and it worked great.

Our only problem is the danged compiler. If you look at figure 1 of
the DS099-2.pdf thing, it sure looks like all the wires I want are
there. In fact, if we can take this diagram literally, the ttl
tristate driver is already connected to one pin of the LVDS receiver.

I'd still like to know why John needs to mix LVDS and a single-ended output.
It's probably something evil or illegal ;-O

Both. It's so terrible that if I told you, The Authorities would take
away my slide rule.

John

As suggested by nospam, you might get what you want using the FPGA
editor. To minimize the amount of fudging, have your ISE schematic
entry person do this:

- Instantiate both pins as IOPAD
- Instantiate IBUFDS with IOSTANDARD=LVDS_25
- instantiate OBUFTDS with IOSTANDARD=LVDS_25
- wire the diff sides of the IBUFDS and OBUFTDS to the IOPADs
- wire the OBUFTDS inputs as if it is your desired OBUFT
- after compilation use FPGA editor to tweak the IOB to make the
output side an OBUFT. You can capture this as a macro for
repeatability and documentation purposes.

Let us know if this works.
Click to expand...
Thanks, Greg.

I'll have the boys try this.

John
 
On Fri, 25 Mar 2005 20:59:11 -0800, John Larkin
<jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:

Hi,

Given a Spartan 3 chip, what I'd like to do is arrange two pins as an
LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable
driver drive one of those pins. From what I know of the output cell
architecture, it looks pretty likely that the hardware resources
exist. My guys are using ISE with schematic entry, and I'm not an ISE
driver, but they say it can't be done, or at least ISE won't let them
do it.

Any ideas? It would be very cool if this would work; it would save us
a bunch of pins and a bunch of picofarads.

Thanks,

John
Click to expand...

Followup:

My guys got it to work.

They configured an LVDS transceiver i/o block, whose output stage is
tristatable. The transmitter side turns out to be not lvds at all, but
a pair of rail-to-rail tristate drivers. So they go into the layout
editor and kluge one of the tristate drivers to permanently disable
it, connecting its \enable to Vcc or something.

Even though it works, it would create such a design maintenance hassle
I think we won't do it.

John
 
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