Characterizing the pll

[nagendra]

hi,
i am working on pll design.i have designed charge pump pll.
could any one tell me how to characterize it ? means how to messure
jitter (long term, short term and lock range etc).
i am using cadence spectre for simulation.
looking forward to reply

 

[John Gianni]

nagendra wrote:

i am working on pll design.i have designed charge pump pll.
could any one tell me how to characterize it ? means how to messure
jitter (long term, short term and lock range etc).
i am using cadence spectre for simulation.
looking forward to reply

I was going to suggest picking up the Cadence Hummingbird PLL if you
are a university student. But I see you already posted the exact same
question to the crete_users group. Therefore, for the benefit of
others, I'll quickly note that Crete supplies designs, design kits ,
and documented flows which include simple analysis methods for each
device, including the parasitic extraction & resimulation.

In addition, check out Ken Kundert's and Henry Chang's Designer's Guide
Consulting http://www.designers-guide.com & the original
http://www.designers-guide.org site for papers on this topic, for
example http://www.designers-guide.org/Analysis/PLLjitter.pdf

See also Cadence articles on the topic, for example,
http://www.cadence.com/whitepapers/jitter.pdf
http://www.cadence.com/community/virtuoso/resources/CICC04_4thOrderDualPath.pdf

John Gianni
-- Nothing stated by me on the USENET is prior reviewed by my employer!

 

[John Gianni]

I'll quickly note that Crete supplies designs, design kits ,
and documented flows which include simple analysis methods for each
device, including the parasitic extraction & resimulation.

I forgot to provide the reference to the Cadence University Program web
site, which is http://crete.cadence.com

They support both analog and digital curriculums with their designs,
design kits, and documentation (please see the license agreement at
that site).

If you have questions, you can mail them at the address "crete" at the
domain cadence dot com.

As always, post hints to help others & good luck in all that you do,

John Gianni
-- Nothing stated by me on the USENET is prior reviewed by my employer!

 

[nagendra]

hi john,

thanks for ur suggestio. but be specific could you explain me how
to measure jitter
using pnoise analysis (transistor level schematic.)
i have done spss analysis sucessfully, but for pnoise what value should
be set for
parameter - output, input, noise type.
actually i did pnoise as setting output as voltage( vco ouput as
positive net and gnd as negative net), no input , and noise type jitter
with threshold value for either 0 , 1 or any value less than pick of
vco o/p.
but pnoise analysis has been terminated , with message as no crossing
event found.
i don't no how to cope with this problem , could you suggest me to find
out where i had done wrong. or there is any other method to find jitter
of whole pll.

i have wasted alot of time on this. transient results are quite good,
as i checked by making divider ratio 1, so the same input and output
frequecy for PLL. result are very exciteing, asat all conrners rising
edge of both input and output waveform (since i/p is square wave) is
matched when pll locks.

sorry if i bored you.

thanks in advance,

Nagendra

 

[Andrew Beckett]

On 15 Feb 2006 05:01:23 -0800, "nagendra" <nagendra.iitd@gmail.com> wrote:

hi john,

thanks for ur suggestio. but be specific could you explain me how
to measure jitter
using pnoise analysis (transistor level schematic.)
i have done spss analysis sucessfully, but for pnoise what value should
be set for
parameter - output, input, noise type.
actually i did pnoise as setting output as voltage( vco ouput as
positive net and gnd as negative net), no input , and noise type jitter
with threshold value for either 0 , 1 or any value less than pick of
vco o/p.
but pnoise analysis has been terminated , with message as no crossing
event found.
i don't no how to cope with this problem , could you suggest me to find
out where i had done wrong. or there is any other method to find jitter
of whole pll.

i have wasted alot of time on this. transient results are quite good,
as i checked by making divider ratio 1, so the same input and output
frequecy for PLL. result are very exciteing, asat all conrners rising
edge of both input and output waveform (since i/p is square wave) is
matched when pll locks.

sorry if i bored you.

thanks in advance,

Nagendra

Read the paper that John referenced on the Designer's Guide site. It covers this
pretty thoroughly.

It discusses the difficulty of doing PSS on a PLL, and gives an approach to
break down the PLL into components which can be separately characterised.

There's no 30 second answer (certainly with no knowledge of your circuit), so
please do read the information; it's an excellent paper.

Andrew.

 

[John Gianni]

Nagendra S. Chandrakar asked:

thanks for ur suggestio. but be specific could you explain me how
to measure jitter using pnoise analysis (transistor level schematic.)

Andrew Beckett advised:

Read the paper that John referenced on the Designer's Guide site.
It covers this pretty thoroughly.

In addition, I have recently seen a new (draft status) application note
describing the basic PLL jitter measurement flow running specifically
on one of the 90nm PLLs I developed in the past.

If you contact your Customer Support representative for the Spectre RF
tool, they can perhaps send you this draft apnote for your review.
Please bear in mind, you have to prior know how to run pnoise before
you avail yourself of the utility of the apnote. Much of what you need
will be in the basic SpectreRF User Guide (which covers a variety of
pnoise analysis applications).

Interestingly, the PLL used for this draft application note on the
basic jitter flow is the same 90nm PLL (schematic, layout, testbenches,
etc.) supplied in the Cadence Methodology Kit which, if you've seen the
press reports, is a new offering available on
http://www.downloads.cadence.com for those who have purchased the
license. Your sales team can help you with the determination if that is
something you'll benefit from.

In addition, I see you've received some expert help on the crete_users
group which should be posted back here so that the record (for others
to benefit) is more complete.

Good luck,

John Gianni
-- Nothing stated by me on the USENET is prior reviewed by my employer.
-- The email address above is a spam trap; please do not expect a
private response.

 

[John Gianni]

Copied from http://crete.cadence.com users for others to benefit:

Hi Nagendra,
Here is a little more info,
Theoretically speaking lock range has a formula
(lock range = 4*pi*damping factor*wn)
where wn is natural frequency,damping factor =(wn/2* R2.C) where R2 and
C are connected in series in the filter.

Practically we can define lock range as the range of input frequency for
which the pll locks.For eg: if the pll locks in the range of input
frequency from 800 to 1200 Hz where the input signal is a 1 kHz signal
then we can say that the lock range is 200hz.So to check the lock range
while doing simulations you can see for what range of the input
frequencies the PLL will lock.

There is a book called CMOS circuit design,layout and simulation by R
Jacob Baker which has a chapter on PLL design (chapter 19 ) which has
more info on jitter and lock range.