Change GENERICS at top level for synthess

[Andy Luotto]

Hi there

I am going to sinthesize a design using different generic value for
synthesis and simulation.

To be precise, I was using DW memories for simulation (which are
limited to 256 depth))) and memory macrocell for synthesis and
implmentation.
Is there a way to force a generic value from Synopsys DC before
elaboration in order to force the toll to assign the right values? I
can do it easily during simulation using configuration bt Synopsys does
not support configuration (I never understood why ...)

Thanks

 

[Nicolas Matringe]

Andy Luotto a écrit :

Hi there

I am going to sinthesize a design using different generic value for
synthesis and simulation.
[...]
Is there a way to force a generic value from Synopsys DC before
elaboration in order to force the toll to assign the right values? I
can do it easily during simulation using configuration bt Synopsys does
not support configuration (I never understood why ...)

Hello
Why don't you assign simulation values to your generics in your
testbench (where you instantiate your top-level design file), keeping
default values for synthesis? (see example below)

entity top_level is
generic (
GEN_PARAM : natural := synthesis_default_value_1);
....

entity testbench
....
architecture str of testbench is
....
top_level_inst : top_level
generic map (
GEN_PARAM => simulation_value_1)
....

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Andy Luotto]

Nicolas Matringe wrote:

Andy Luotto a écrit :
Hi there

I am going to sinthesize a design using different generic value for
synthesis and simulation.
[...]
Is there a way to force a generic value from Synopsys DC before
elaboration in order to force the toll to assign the right values?
I
can do it easily during simulation using configuration bt Synopsys
does
not support configuration (I never understood why ...)

Hello
Why don't you assign simulation values to your generics in your
testbench (where you instantiate your top-level design file), keeping

default values for synthesis? (see example below)

entity top_level is
generic (
GEN_PARAM : natural := synthesis_default_value_1);
...

entity testbench
...
architecture str of testbench is
...
top_level_inst : top_level
generic map (
GEN_PARAM => simulation_value_1)
...

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

Good idea. Thanks (the simple the better!

Cheers