Change a logic value in the middle of verilog simulation

[teacupfull business]

Hi, we were trying to model soft error effect in verilog testbench.

The behavior of soft error is: you instantly flip a value at a DFF Q
pin from "1 to 0" or "0 to 1".
We were initially try to use force:
If the original value is 0, we force the value to 1; and then release
it and let it run.

But we found it doesn't work, since one released, the Q pin can not
keep the forced value.
Any suggestions?

 

[Jonathan Bromley]

On Mon, 26 Apr 2010 12:31:10 -0700 (PDT), gabor <gabor@alacron.com>
wrote:

On Apr 26, 3:16 pm, teacupfull business
teacupfull.busin...@gmail.com> wrote:
Hi, we were trying to model soft error effect in verilog testbench.

The behavior of soft error is: you instantly flip a value at a DFF Q
pin from "1 to 0" or "0 to 1".
We were initially try to use force:
If the original value is 0, we force the value to 1; and then release
it and let it run.

But we found it doesn't work, since one released, the Q pin can not
keep the forced value.
Any suggestions?

I think you have to run after forcing before you release the signal
otherwise I'm not sure how the flip-flop would toggle. It shouldn't
matter how long you keep it forced, assuming you don't expect a
normal logic event like an enabled clock edge to change he value back.
Did you try forcing the value, running for 1 ps (or whatever the
simulation resolution is) and then releasing it?

All true, but it's also possible that the OT is trying to force
a net that's the buffered output from something; in which
case, as soon as it's released, it'll go back to the value
driven on to it from the original reg.

--
Jonathan Bromley

 

[gabor]

On Apr 26, 3:16 pm, teacupfull business
<teacupfull.busin...@gmail.com> wrote:

Hi, we were trying to model soft error effect in verilog testbench.

The behavior of soft error is: you instantly flip a value at a DFF Q
pin from "1 to 0" or "0 to 1".
We were initially try to use force:
If the original value is 0, we force the value to 1; and then release
it and let it run.

But we found it doesn't work, since one released, the Q pin can not
keep the forced value.
Any suggestions?

I think you have to run after forcing before you release the signal
otherwise I'm not sure how the flip-flop would toggle. It shouldn't
matter how long you keep it forced, assuming you don't expect a
normal logic event like an enabled clock edge to change he value back.
Did you try forcing the value, running for 1 ps (or whatever the
simulation resolution is) and then releasing it?

 

[Muzaffer Kal]

On Mon, 26 Apr 2010 12:16:58 -0700 (PDT), teacupfull business
<teacupfull.business@gmail.com> wrote:

Hi, we were trying to model soft error effect in verilog testbench.

The behavior of soft error is: you instantly flip a value at a DFF Q
pin from "1 to 0" or "0 to 1".
We were initially try to use force:
If the original value is 0, we force the value to 1; and then release
it and let it run.

But we found it doesn't work, since one released, the Q pin can not
keep the forced value.
Any suggestions?

What you can do is to force the D of the flop and wait for a clock
signal to arrive to release it. This will load an arbitrary value to
the flop for one clock cycle.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

teacupfull.busin...@gmail.com> wrote:
Hi, we were trying to model soft error effect in verilog testbench.

But we found it doesn't work, since one released, the Q pin can not
keep the forced value.
Any suggestions?

Forcing the output pin doesn't do any good, since that isn't the
memory element holding the state. As soon as you release it, the
value from the output driver of the flop will reassert itself.

Instead, you should find the memory element holding the state, and
overwrite that. In a behavioral model, this will be a reg or
variable. Simply assigning to it should change the state, without any
need for a force. Note that for a reg that is declared as an output
port of a module, the reg inside the module is a different thing from
the net it drives outside the module.

If this flop is modeled with a UDP, then you are out of luck, since
the internal state is not accessible from outside (except maybe with
VPI).