Change a constant value, depending on a generic

B

Barry

Guest
Is there a more clever and compact way to do this, rather than writing
a function? The constant INIT_40_VAL is assigned to a generic in a
component instantiation later on.
TIA


entity v5_sysmon is
generic ( SIM_ONLY : integer := 0 ); -- = 1 to set averaging to 1
instead of 16
......

architecture rtl of v5_sysmon is

function set_init_40(sim_only : in integer) return bit_vector is
constant init_40_avg1 : bit_vector := X"0000";
constant init_40_avg16 : bit_vector := X"1000";
begin
if sim_only = 1 then
return init_40_avg1;
else
return init_40_avg16;
end if;
end function set_init_40;

constant INIT_40_VAL : bit_vector := set_init_40(SIM_ONLY);
 
On Jan 13, 12:34 pm, Barry <barry...@gmail.com> wrote:
Is there a more clever and compact way to do this, rather than writing
a function?  The constant INIT_40_VAL is assigned to a generic in a
component instantiation later on.
TIA

entity v5_sysmon is
  generic ( SIM_ONLY : integer := 0 );   --  = 1 to set averaging to 1
instead of 16
.....

architecture rtl of v5_sysmon is

  function set_init_40(sim_only : in integer) return bit_vector is
    constant init_40_avg1  : bit_vector := X"0000";
    constant init_40_avg16 : bit_vector := X"1000";
  begin
    if sim_only = 1 then
      return init_40_avg1;
    else
      return init_40_avg16;
    end if;
  end function set_init_40;

  constant INIT_40_VAL : bit_vector := set_init_40(SIM_ONLY);
First, I wouldn't use types bit and bit_vector, but instead std_logic,
std_logic_vector, and signed and unsigned from ieee.numeric_std.

How about:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity v5_sysmon is
generic ( SIM_ONLY : integer range 0 to 1 := 0 );
....
end entity;

architecture rtl of v5_sysmon is

constant INIT_40 : std_logic_vector(15 downto 0) := std_logic_vector
(to_unsigned(4096 * SIM_ONLY), 16);

-- rest of code

Dave
 
On Jan 13, 9:53 am, Dave <dhsch...@gmail.com> wrote:
On Jan 13, 12:34 pm, Barry <barry...@gmail.com> wrote:





Is there a more clever and compact way to do this, rather than writing
a function?  The constant INIT_40_VAL is assigned to a generic in a
component instantiation later on.
TIA

entity v5_sysmon is
  generic ( SIM_ONLY : integer := 0 );   --  = 1 to set averaging to 1
instead of 16
.....

architecture rtl of v5_sysmon is

  function set_init_40(sim_only : in integer) return bit_vector is
    constant init_40_avg1  : bit_vector := X"0000";
    constant init_40_avg16 : bit_vector := X"1000";
  begin
    if sim_only = 1 then
      return init_40_avg1;
    else
      return init_40_avg16;
    end if;
  end function set_init_40;

  constant INIT_40_VAL : bit_vector := set_init_40(SIM_ONLY);

First, I wouldn't use types bit and bit_vector, but instead std_logic,
std_logic_vector, and signed and unsigned from ieee.numeric_std.

How about:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity v5_sysmon is
   generic ( SIM_ONLY : integer range 0 to 1 := 0 );
...
end entity;

architecture rtl of v5_sysmon is

constant INIT_40 : std_logic_vector(15 downto 0) := std_logic_vector
(to_unsigned(4096 * SIM_ONLY), 16);

-- rest of code

Dave- Hide quoted text -

- Show quoted text -
Thanks, Dave. Type bit_vector is used to match the type of the
generic in the Xilinx unisim component "SYSMON" (not shown in my
snippet).
 
On 13 Jan, 17:34, Barry <barry...@gmail.com> wrote:
Is there a more clever and compact way to do this, rather than writing
a function?  The constant INIT_40_VAL is assigned to a generic in a
component instantiation later on.
TIA

entity v5_sysmon is
  generic ( SIM_ONLY : integer := 0 );   --  = 1 to set averaging to 1
instead of 16
.....

architecture rtl of v5_sysmon is

  function set_init_40(sim_only : in integer) return bit_vector is
    constant init_40_avg1  : bit_vector := X"0000";
    constant init_40_avg16 : bit_vector := X"1000";
  begin
    if sim_only = 1 then
      return init_40_avg1;
    else
      return init_40_avg16;
    end if;
  end function set_init_40;

  constant INIT_40_VAL : bit_vector := set_init_40(SIM_ONLY);
This is the most compact form for anything more complicated than
arithmatic. What is good about this though is it allows you to put
assertions in the function that can check the validity of generics and
or combinations of generics so that in some synthesisers (not that
many actually) you can halt synthesis and simulation.
 
For some applications (maybe not yours, since the generic has 2^32
possible values), a constant array indexed by the generic would be
simpler than a function.

-- the array typedef
type init_40_choice_t is array (integer range <>) of bit_vector(15
downto 0);

-- the (really big) array:
constant init_40_choices : init_40_choice_t(integer'range)
:= (1 => X"0000",
others => X"1000");
-- index the array with the generic
constant init_40_val : bit_vector := init_40_choices(sim_only);

Hope this helps,

Andy
 
On Tue, 13 Jan 2009 09:34:10 -0800 (PST), Barry <barry374@gmail.com>
wrote:

Is there a more clever and compact way to do this, rather than writing
a function? The constant INIT_40_VAL is assigned to a generic in a
component instantiation later on.
TIA


entity v5_sysmon is
generic ( SIM_ONLY : integer := 0 ); -- = 1 to set averaging to 1
The first question is: why on earth would you use an integer where a
boolean is so clearly called for?
(the only reason I can think of is too much brain-rotting C :)

generic ( SIM_ONLY : boolean := FALSE );
Put this together with Andy's suggestion and you have

constant array set_init_40(boolean) of bit_vector := (X"0000", X"1000");
or MUCH BETTER to make it crystal clear

constant array set_init_40(boolean) of bit_vector :=
( FALSE => X"0000",
TRUE => X"1000");

and the usage remains the same...

constant INIT_40_VAL : bit_vector := set_init_40(SIM_ONLY);
How do I extend it to three (or seven or ...) cases?
Easy; boolean is just an enumeration; define your own and use that
instead.

type colour is (red, green, blue);

constant array gain (colour) of integer := (red => 31, green =>58,
blue =>11);

red_channel <= video_in * gain(red);

type weekday is (monday, -- you get the picture...

- Brian
 
On Jan 15, 4:26 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
On Tue, 13 Jan 2009 09:34:10 -0800 (PST), Barry <barry...@gmail.com
wrote:



The first question is: why on earth would you use an integer where a
boolean is so clearly called for?
(the only reason I can think of is too much brain-rotting C :)
The generic SIM_ONLY originally came from the code produced by the
Xilinx MIG for my SDRAM controller. I am re-using it here for another
purpose, so that I only have a single "only for simulation" generic to
keep track of at the testbench level. I don't care to re-write all of
the MIG-produced code modules for a boolean generic. Otherwise, you
offer a nice solution.

The original solution with a function is fine; sometimes I learn
something really clever in the newsgroups that I had not thought of
before, so I just figured I would ask.

Barry
 
On Thu, 15 Jan 2009 09:56:29 -0800 (PST), Barry <barry374@gmail.com>
wrote:

On Jan 15, 4:26 am, Brian Drummond <brian_drumm...@btconnect.com
wrote:

The first question is: why on earth would you use an integer where a
boolean is so clearly called for?
(the only reason I can think of is too much brain-rotting C :)


The generic SIM_ONLY originally came from the code produced by the
Xilinx MIG for my SDRAM controller.
I stand by my comments then! :)

But thanks for the warning, I have a MIG project coming up soon.
(Mig 2.3) Initial impression is that it's hugely improved over Mig 1.6,
which I decided I couldn't work with.

- Brian
 
Barry wrote:

The generic SIM_ONLY originally came from the code produced by the
Xilinx MIG for my SDRAM controller. I am re-using it here for another
purpose, so that I only have a single "only for simulation" generic to
keep track of at the testbench level.
I use this...

constant in_simulation : BOOLEAN := false
-- synthesis translate_off
or true
-- synthesis translate_on
;
constant in_synthesis : boolean := not in_simulation;

....in a global package so that I don't have to worry about explicitly
setting such constants during simulation/synthesis.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 

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