Challenges

What are the challenges of using Verilog compared to other HDL's?
I guess it is with multiple levels of abstraction.. Also can anyone
give an example of conflicting constraints in Verilog..

Thanks

 

[Mike Treseler]

1stderivative@gmail.com wrote:

What are the challenges of using Verilog compared to other HDL's?
limiting variable scope
I guess it is with multiple levels of abstraction.. Also can anyone
give an example of conflicting constraints in Verilog..
Whether or not to help with homework problems.