K
Khaled
Guest
************************************************************************
CALL FOR PAPERS
The 3rd International Workshop on
Highly Efficient Accelerators and Reconfigurable Technologies
-- HEART2012 --
Okinawa, Japan
May 30 - June 1, 2012
<http://www.isheart.org>
************************************************************************
IMPORTANT DATES (UTC):
- Paper submission: February 21, 2012
- Author notification: March 26, 2012
- Design contest entry: March 26, 2012
- Camera-ready due: April 12, 2012
- Design contest: May 30, 2012
- Workshop date: May 31 - June 1, 2012
The 3rd International Workshop on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
new research on accelerators and the use of reconfigurable
technologies for high-performance and/or power-efficient
computation. Submissions are solicited on a wide variety of topics
related to the acceleration for high-performance computation,
including but not limited to:
* Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA,
GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core architectures, NoC
architectures, 3D-stacking technologies and optical devices
* Software and applications:
- Novel applications for efficient acceleration systems/platforms,
and custom computing
- Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the
program committee will provide higher priority for papers that present
highly innovative and challenging ideas.
We will accept regular and short papers for oral and poster
presentation, respectively. All the accepted regular papers will be
published in the post-proceedings that will be published as a
special issue of ACM SIGARCH Computer Architecture News (CAN) and
will also be available in ACM Digital Library. By submitting your work
to the HEART2012 workshop, you grant permission for ACM to publish the
material in print and digital formats in ACM's Computer Architecture
News and the ACM archive. The short papers will be included in the
workshop handout distributed at the workshop. One of the authors must
attend the workshop and present their work as a condition of
publication.
All papers must be no more than 6 pages (two columns, US letter size,
10 points for main body text) in length and prepared in PDF
format. For double-blind review, manuscripts must NOT identify
authors; names of authors, affiliations, e-mail addresses and
self-references should be blanked out. Papers that identify authors
may be rejected without review. Full formatting and submission
instructions are available at the HEART2012 web-site.
For more information, please visit <http://www.isheart.org/>.
In addition to the presentation of accepted papers, we will also have
two keynote lectures. The detail of the workshop program will be
available soon at the HEART2012 WEB site.
Moreover, we will hold the FPGA design-contest "Connect6 Revenge" on
30 May, 2012, in conjunction with the technical committee on
reconfigurable Systems (RECONF) of IEICE, Japan. The awards ceremony
of the contest will be held at the welcome reception on 30
May. Contest participants are required to register by following
instructions at
<http://www.cs.tsukuba.ac.jp/~yoshiki/FPGA/Contest_eng/index.php>.
Workshop Committees
-------------------
Workshop Co-chairs:
- Hideharu Amano, Keio University, JP
- Wayne Luk, Imperial College London, UK
Program Co-chairs:
- Walid Najjar, University of California Riverside, US
- Yukinori Sato, JAIST, JP
- David Thomas, Imperial College London, UK
Publication Co-chairs:
- Yuichiro Shibata, Nagasaki University, JP
- Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
Publicity Co-chairs:
- Yoshiki Yamaguchi, University of Tsukuba, JP
- Khaled Benkrid, the University of Edinburgh, UK
- Qiang Liu, Tianjin University, CN
Finance Chair:
- Kentaro Sano, Tohoku University, JP
Local Arrangement Chair:
- Yasunori Osana, University of Ryukyu, JP
Design Contest Co-chairs:
- Tomonori Izumi, Ritsumeikan University, JP
- Minoru Watanabe, Shizuoka University, JP
Program Committee:
- Ali Akoglu, University of Arizona, US
- Bharat Sukhwani, IBM T. J. Watson Research Center, US
- Chiwai Yu, City University of Hong Kong, Hong Kong, HK
- Dirk Koch, University of Oslo, NO
- Florent de Dinechin, Ecole Normale Superieure de Lyon, FR
- Gregory Peterson, University of Tenessee, US
- Hayden Kwok-Hay So, University of Hong Kong, HK
- Henry Styles, Xilinx, US
- Herman Lam, University of Florida, US
- Martin Herbordt, Boston University, US
- Masato Yoshimi, Doshisha University, JP
- Miquel Pericas, Tokyo Institute of Technology, JP
- Nachiket Kapre, Imperial College London, UK
- Paolo Ienne, EPFL, CH
- Philip Brisk, University of California, Riverside, US
- Philip Leong, University of Sydney, AU
- Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
- Stephan Wong, Delft University of Technology, NL
- Thomas D. VanCourt, Akamai Technologies, US
- Tsutomu Maruyama, University of Tsukuba, JP
- Wim Vanderbauwhede, Glasgow University, UK
- Yajun Ha, National University of Singapore, SG
- Yiannis Sourdis, Chalmers University of Technology, SE
- Yohei Hori, National Institute of Advanced Industrial Science and
Technology, JP
************************************************************************
CALL FOR PAPERS
The 3rd International Workshop on
Highly Efficient Accelerators and Reconfigurable Technologies
-- HEART2012 --
Okinawa, Japan
May 30 - June 1, 2012
<http://www.isheart.org>
************************************************************************
IMPORTANT DATES (UTC):
- Paper submission: February 21, 2012
- Author notification: March 26, 2012
- Design contest entry: March 26, 2012
- Camera-ready due: April 12, 2012
- Design contest: May 30, 2012
- Workshop date: May 31 - June 1, 2012
The 3rd International Workshop on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
new research on accelerators and the use of reconfigurable
technologies for high-performance and/or power-efficient
computation. Submissions are solicited on a wide variety of topics
related to the acceleration for high-performance computation,
including but not limited to:
* Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA,
GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core architectures, NoC
architectures, 3D-stacking technologies and optical devices
* Software and applications:
- Novel applications for efficient acceleration systems/platforms,
and custom computing
- Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the
program committee will provide higher priority for papers that present
highly innovative and challenging ideas.
We will accept regular and short papers for oral and poster
presentation, respectively. All the accepted regular papers will be
published in the post-proceedings that will be published as a
special issue of ACM SIGARCH Computer Architecture News (CAN) and
will also be available in ACM Digital Library. By submitting your work
to the HEART2012 workshop, you grant permission for ACM to publish the
material in print and digital formats in ACM's Computer Architecture
News and the ACM archive. The short papers will be included in the
workshop handout distributed at the workshop. One of the authors must
attend the workshop and present their work as a condition of
publication.
All papers must be no more than 6 pages (two columns, US letter size,
10 points for main body text) in length and prepared in PDF
format. For double-blind review, manuscripts must NOT identify
authors; names of authors, affiliations, e-mail addresses and
self-references should be blanked out. Papers that identify authors
may be rejected without review. Full formatting and submission
instructions are available at the HEART2012 web-site.
For more information, please visit <http://www.isheart.org/>.
In addition to the presentation of accepted papers, we will also have
two keynote lectures. The detail of the workshop program will be
available soon at the HEART2012 WEB site.
Moreover, we will hold the FPGA design-contest "Connect6 Revenge" on
30 May, 2012, in conjunction with the technical committee on
reconfigurable Systems (RECONF) of IEICE, Japan. The awards ceremony
of the contest will be held at the welcome reception on 30
May. Contest participants are required to register by following
instructions at
<http://www.cs.tsukuba.ac.jp/~yoshiki/FPGA/Contest_eng/index.php>.
Workshop Committees
-------------------
Workshop Co-chairs:
- Hideharu Amano, Keio University, JP
- Wayne Luk, Imperial College London, UK
Program Co-chairs:
- Walid Najjar, University of California Riverside, US
- Yukinori Sato, JAIST, JP
- David Thomas, Imperial College London, UK
Publication Co-chairs:
- Yuichiro Shibata, Nagasaki University, JP
- Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
Publicity Co-chairs:
- Yoshiki Yamaguchi, University of Tsukuba, JP
- Khaled Benkrid, the University of Edinburgh, UK
- Qiang Liu, Tianjin University, CN
Finance Chair:
- Kentaro Sano, Tohoku University, JP
Local Arrangement Chair:
- Yasunori Osana, University of Ryukyu, JP
Design Contest Co-chairs:
- Tomonori Izumi, Ritsumeikan University, JP
- Minoru Watanabe, Shizuoka University, JP
Program Committee:
- Ali Akoglu, University of Arizona, US
- Bharat Sukhwani, IBM T. J. Watson Research Center, US
- Chiwai Yu, City University of Hong Kong, Hong Kong, HK
- Dirk Koch, University of Oslo, NO
- Florent de Dinechin, Ecole Normale Superieure de Lyon, FR
- Gregory Peterson, University of Tenessee, US
- Hayden Kwok-Hay So, University of Hong Kong, HK
- Henry Styles, Xilinx, US
- Herman Lam, University of Florida, US
- Martin Herbordt, Boston University, US
- Masato Yoshimi, Doshisha University, JP
- Miquel Pericas, Tokyo Institute of Technology, JP
- Nachiket Kapre, Imperial College London, UK
- Paolo Ienne, EPFL, CH
- Philip Brisk, University of California, Riverside, US
- Philip Leong, University of Sydney, AU
- Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
- Stephan Wong, Delft University of Technology, NL
- Thomas D. VanCourt, Akamai Technologies, US
- Tsutomu Maruyama, University of Tsukuba, JP
- Wim Vanderbauwhede, Glasgow University, UK
- Yajun Ha, National University of Singapore, SG
- Yiannis Sourdis, Chalmers University of Technology, SE
- Yohei Hori, National Institute of Advanced Industrial Science and
Technology, JP
************************************************************************