cdsSpice Early Termination

[michael_skoufis]

I try to simulate a fairly large digital circuit using Transient Analysis
for about 40-50 ns. When I try to simulate components of the circuit
separately, Transient Analysis completes normally. When I try to run DC
Analysis for the whole circuit it also works. However, Transient Analysis
run for 50 ns for the whole circuit always terminates after 1 ns about.

I tried to change the tolerances (Absolute & Relative) and some other
parameters. I was able to expand the simulation window to the requested
time (50 ns) but the output makes no sense. It jumps from -60 KV (!!!) to
0 and stays there throughout the whole simulation time.

Anyone has a clue how to fix this?

Mike

 

[Svenn Are Bjerkem]

On Nov 8, 6:34 pm, "michael_skoufis" <skouf1...@nospam.yahoo.com>
wrote:

I try to simulate a fairly large digital circuit using Transient Analysis
for about 40-50 ns. When I try to simulate components of the circuit

Is the digital circuit created "full custom" in cadence or is it a gate
netlist from a synthesis program?

What is your driving testbench looking like? Do you have any current
sources that are not properly loaded all the time?

--
Svenn

 

[michael_skoufis]

It's a custom IC design using nmos, pmos and voltage sources. Everything
seems to be fine as far as source connection. The output of the function
seems to explode to large values. In order for cdsSpice to satisfy the
internal tolerances it reduces the timestep. However, reducing it to
extremely small intervals causes simulator to quit.

Michael

 

[Svenn Are Bjerkem]

michael_skoufis wrote:

It's a custom IC design using nmos, pmos and voltage sources. Everything
seems to be fine as far as source connection. The output of the function
seems to explode to large values. In order for cdsSpice to satisfy the
internal tolerances it reduces the timestep. However, reducing it to
extremely small intervals causes simulator to quit.

Do you happen to have another spice simulator that you could cross
check with? When the timesteps are reduced without any reason, my
experience has been that something is oscillating. It is not nescessary
the circuit itself that is oscillating but it can also be the simulator
itself. When you get values in the range of kV in a CMOS circuit it is
in my circuits most often a current source that is not properly loaded
because the load gets shut off. I am running out of ideas as I don't
have any experience with cdsSpice, just spectre. Maybe it is time for a
phone to Cadence support?

--
Svenn

 

[michael_skoufis]

Thanks a lot for your responses Svenn, I just needed to change some
tolerances (Absolute, Relative and Charge) in the cdsSpice setup table.
Now it's all fine.


Mike