CD4017 chip output latching problem

HI all,

I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long.
For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive?
It's driving me nuts.

TIA

 

On Sunday, 9 December 2012 16:53:42 UTC+1, orion....@virgin.net wrote:

HI all,



I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long.

For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive?

It's driving me nuts.



TIA

I should just mention that if you're one of the people that suggested tips on the previous thread in relation to this issue, I have tried them all to know avail.

 

[David Eather]

On Mon, 10 Dec 2012 01:56:06 +1000, <orion.osiris@virgin.net> wrote:

On Sunday, 9 December 2012 16:53:42 UTC+1, orion....@virgin.net wrote:
HI all,



I've been having problems with a timer circuit I'm building. It uses a
chain of seven CD4017BE decade counters. The first in the chain gets
clock pulses from a 555 running at about 10Hz. I take the last output
from this chip (puts out one pulse for every 10 input pulses) and feed
it to the input of the next chip where the same thing is done and so on
so the pulses get time-divided by 10 at each stage. All's fine up to
decade 4, then something odd happens. Instead of just pulsing, the
output goes high and remains high until the next pulse comes along and
toggles it back to low, so this stage's output is high for far too long.

For this prototype I'm using rat's nest on PCB construction and believe
I've paid proper attention to grounding and decoupling. Funny thing is,
if I transfer the components over to proto-board, the problem
disappears. Do these symptoms ring a bell with anyone? Is the 4017
particularly layout-sensitive?

It's driving me nuts.



TIA

I should just mention that if you're one of the people that suggested
tips on the previous thread in relation to this issue, I have tried them
all to know avail.

I don't know what is going wrong - the 4000 series cmos is pretty much
trouble free and so is the 4017 (disregard the guy who said the 4017
causes glitches - it does not. A 555 might)

 

[John Fields]

On Sun, 9 Dec 2012 07:56:06 -0800 (PST), orion.osiris@virgin.net
wrote:

On Sunday, 9 December 2012 16:53:42 UTC+1, orion....@virgin.net wrote:
HI all,



I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long.

For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive?

It's driving me nuts.

---
If you're using a bipolar 555, then it's _mandatory_ that you connect
about a 100nF low ESR cap directly across pins 1 and 8 in order to
keep the 555's shoot-through switching transient from sucking the Vcc
rail down.

Also, since you're not seeing the problem on your proto board layout,
there's obviously something wrong with your rat's nest layout.

If it were me pulling that plow, I'd blow off the 555 and go CMOS.


--
JF

 

Well, I did read that the 555 is a bit of a current hog during switching, so I've used a 100uF electrolytic across pins 1 & 8 of it and hoping that - whilst not optimal - will do. Tomorrow I'll make up another pcb with a different trace layout and see if that cures it.

 

[ehsjr]

On 12/9/2012 6:18 PM, orion.osiris@virgin.net wrote:

Well, I did read that the 555 is a bit of a current hog during switching, so I've used a 100uF electrolytic across pins 1 & 8 of it and hoping that - whilst not optimal - will do. Tomorrow I'll make up another pcb with a different trace layout and see if that cures it.

Use 100 _nf_ not 100 _uf_

Ed

 

[Jasen Betts]

On 2012-12-10, ehsjr <ehsjr@nospamverizon.net> wrote:

On 12/9/2012 6:18 PM, orion.osiris@virgin.net wrote:
Well, I did read that the 555 is a bit of a current hog during switching, so I've used a 100uF electrolytic across pins 1 & 8 of it and hoping that - whilst not optimal - will do. Tomorrow I'll make up another pcb with a different trace layout and see if that cures it.


Use 100 _nf_ not 100 _uf_

I second that motion!

a 100nF polyester or ceramic capacitor will have a much lower resistance than an
electrolytic capacitor, and that's important for decoupling power
supplies


--
⚂⚃ 100% natural

--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

 

Yes, not to mention much lower parasitic inductance to boot! Perhaps a 100uF electrolytic AND a 100nF ceramic in parallel would be the best solution?
BTW, have now discovered that the inputs to each 4017 stage must have pull-down resistors. Didn't know that; could be the source of the problem. I'm going to carry out the necessary mods and try it out again.
Thanks, all.

 

[John Fields]

On Tue, 11 Dec 2012 00:39:12 -0800 (PST), orion.osiris@virgin.net
wrote:

Yes, not to mention much lower parasitic inductance to boot! Perhaps a 100uF electrolytic AND a 100nF ceramic in parallel would be the best solution?
BTW, have now discovered that the inputs to each 4017 stage must have pull-down resistors. Didn't know that; could be the source of the problem. I'm going to carry out the necessary mods and try it out again.
Thanks, all.

---
You should leave a little of the message you're replying to intact in
order to preserve the context and allow us to know what you're
replying to.

--
JF

 

On Tuesday, 11 December 2012 13:31:11 UTC+1, John Fields wrote:

On Tue, 11 Dec 2012 00:39:12 -0800 (PST), orion.osiris@virgin.net

wrote:



Yes, not to mention much lower parasitic inductance to boot! Perhaps a 100uF electrolytic AND a 100nF ceramic in parallel would be the best solution?

BTW, have now discovered that the inputs to each 4017 stage must have pull-down resistors. Didn't know that; could be the source of the problem. I'm going to carry out the necessary mods and try it out again.

Thanks, all.



---

You should leave a little of the message you're replying to intact in

order to preserve the context and allow us to know what you're

replying to.



--

JF

Sorry John. I do try to but I'm using the Google Groups interface and it's rubbish. I really shout re-install Agent when I get a minute!