S
sergey
Guest
Hi all again,
Probably a stupid question, but...
I have a signal in my testbench that's "sfixed(X downto -Y)" (sfixed
being signed fixed from David Bishop's fixed-point library).
When I synthesized the actual component, the synthesized model VHDL
converted all of the sfixed to std_logic_vectors.
How do I now map my sfixed in the testbench to std_logic_vector in the
model? (its all just bits of the same length...)
Thanks,
Sergey
Probably a stupid question, but...
I have a signal in my testbench that's "sfixed(X downto -Y)" (sfixed
being signed fixed from David Bishop's fixed-point library).
When I synthesized the actual component, the synthesized model VHDL
converted all of the sfixed to std_logic_vectors.
How do I now map my sfixed in the testbench to std_logic_vector in the
model? (its all just bits of the same length...)
Thanks,
Sergey