casex

[bir]

I have piece of rtl in fifo.

if (write_en && !read_en && !full)
begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
elseif (!write_en && read_en && !empty)
begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
........
.......

can I use a casex statement instead?

casex (write_en, read_en, full, empty)
begin

100x: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01x0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......
endcase

Is this rtl synthesizable??

 

[John_H]

Almost. My syntax would be as follows (I don't know that the "?" works
different than an "x" but it's what I've used).

casex (write_en, read_en, full, empty)
begin
4'b100?: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
4'b01?0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......
endcase


"bir" <ritwikbiswas@gmail.com> wrote in message
news:1163783300.380730.238820@f16g2000cwb.googlegroups.com...

I have piece of rtl in fifo.

if (write_en && !read_en && !full)
begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
elseif (!write_en && read_en && !empty)
begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......
......

can I use a casex statement instead?

casex (write_en, read_en, full, empty)
begin

100x: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01x0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
......
endcase

Is this rtl synthesizable??

 

[John_H]

Sorry... get rid of the first "begin" under the casex.
The casex matches up with the endcase; the first "begin" shouldn't be there.


"John_H" <newsgroup@johnhandwork.com> wrote in message
newsxr7h.5652$Ka1.3927@news01.roc.ny...

Almost. My syntax would be as follows (I don't know that the "?" works
different than an "x" but it's what I've used).

casex (write_en, read_en, full, empty)

/* doesn't belong:

begin
*/

4'b100?: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
4'b01?0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
......
endcase


"bir" <ritwikbiswas@gmail.com> wrote in message
news:1163783300.380730.238820@f16g2000cwb.googlegroups.com...
I have piece of rtl in fifo.

if (write_en && !read_en && !full)
begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
elseif (!write_en && read_en && !empty)
begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......
......

can I use a casex statement instead?

casex (write_en, read_en, full, empty)
begin

100x: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01x0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
......
endcase

Is this rtl synthesizable??

 

[Chris F Clark]

"bir" <ritwikbiswas@gmail.com> writes:

I have piece of rtl in fifo.

if (write_en && !read_en && !full)
begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end
elseif (!write_en && read_en && !empty)
begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......
......

can I use a casex statement instead?

casex (write_en, read_en, full, empty)
begin

100x: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01x0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
......
endcase

Is this rtl synthesizable??

First, you can do what you want with a casex, but a casez is preferred
because if you "accidentally" get an x on one of your signals, the
casex will not treat the x as a don't care. With that it is good to
have a default: wrapped as don't synthesize, to catch if your code is
doing something unexpected.

Second, you need to wrap the four signals in a concatenate to turn
them into one.

Third, as someone else pointed out, your begin after the case is
erroneous.

The code should look more like this:

casez ({write_en, read_en, full, empty})

100x: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01x0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end

.......

(* synthesis off *)
default: begin
$display("No case matched.");
end
(* synthesis on *)

endcase

 

[Plaz]

You're right, except that if you're using a casez, then you should use
'?' (which means 'z', but is more obvious as to what it means in this
context) for the don't-care bits instead of using 'x'.

casez ({write_en, read_en, full, empty})

100?: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01?0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
.......

(* synthesis off *)
default: begin
$display("No case matched.");
end
(* synthesis on *)
endcase

 

[Chris F Clark]

"Plaz" <chris.s.jones@gmail.com> writes:

You're right, except that if you're using a casez, then you should use
'?' (which means 'z', but is more obvious as to what it means in this
context) for the don't-care bits instead of using 'x'.

casez ({write_en, read_en, full, empty})

100?: begin
fifo_reg [write_ptr] <= data_in;
write_ptr<= write_ptr+ 1;
ptr_gap <=ptr_gap + 1;
end

01?0: begin
data_out <= fifo[read_ptr];
read_ptr <= read_ptr+ 1;
ptr_gap <= ptr_gap -1;
end
......

(* synthesis off *)
default: begin
$display("No case matched.");
end
(* synthesis on *)
endcase

You're absolutely right. The point of using casez is that x's don't
represent don't care, so leaving them in the case labels (I can't
recall the verilog term of them) was a bone-head typo error.