case when <subtype> =>

M

MikeWhy

Guest
I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

case fsm_state is
...
when reds_t =&gt; -- illegal, but seems unambiguous enough
case reds_t'(fsm_state) is
when brown =&gt;
fsm_state &lt;= some_state;

when red =&gt;
when orange =&gt;
fsm_state &lt;= some_state;

end case;
when blues_t'low to blues_t'high =&gt; -- wordy, but works
case blues_fsm in
...
end case;
when invalid =&gt;
...
end;


given these declarations:

type state_t is (
black, brown, red, orange,
yellow, green, blue, violet,
gray, white, invalid
);
subtype reds_t is state_t range brown to orange;
subtype blues_t is state_t range green to violet;

signal fsm_state, some_state : state_t;
signal blues_fsm : blues_t;


======
 
Am Freitag, 27. April 2012 06:11:25 UTC+2 schrieb MikeWhy:
I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

case fsm_state is
...
when reds_t =&gt; -- illegal, but seems unambiguous enough
case reds_t'(fsm_state) is
when brown =
fsm_state &lt;= some_state;

when red =
when orange =
fsm_state &lt;= some_state;

end case;
when blues_t'low to blues_t'high =&gt; -- wordy, but works
case blues_fsm in
...
end case;
when invalid =
...
end;


given these declarations:

type state_t is (
black, brown, red, orange,
yellow, green, blue, violet,
gray, white, invalid
);
subtype reds_t is state_t range brown to orange;
subtype blues_t is state_t range green to violet;

signal fsm_state, some_state : state_t;
signal blues_fsm : blues_t;


======
Click to expand...
Hi,
reds_t is just a signal name, but not a value, while blues_t'low represents an actual value.

have you tried what happens when you use

reds_t'range

??

This is often used in loops like
for i in my_slv'range loop
to get this interpreted as e.g.
for i in 31 downto 0 loop

So it might work for the case-when too.


Have a nice synthesis
Eilert
 
&lt;goouse99@googlemail.com&gt; wrote in message
news:11259890.282.1335508094898.JavaMail.geo-discussion-forums@vbvx4...
Am Freitag, 27. April 2012 06:11:25 UTC+2 schrieb MikeWhy:
I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and
some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

case fsm_state is
...
when reds_t =&gt; -- illegal, but seems unambiguous enough
case reds_t'(fsm_state) is
when brown =
fsm_state &lt;= some_state;

when red =
when orange =
fsm_state &lt;= some_state;

end case;
when blues_t'low to blues_t'high =&gt; -- wordy, but works
case blues_fsm in
...
end case;
when invalid =
...
end;


given these declarations:

type state_t is (
black, brown, red, orange,
yellow, green, blue, violet,
gray, white, invalid
);
subtype reds_t is state_t range brown to orange;
subtype blues_t is state_t range green to violet;

signal fsm_state, some_state : state_t;
signal blues_fsm : blues_t;


======

Hi,
reds_t is just a signal name, but not a value, while blues_t'low
represents an actual value.

have you tried what happens when you use

reds_t'range

??

This is often used in loops like
for i in my_slv'range loop
to get this interpreted as e.g.
for i in 31 downto 0 loop

So it might work for the case-when too.
Click to expand...
Hi, yes. XST complains that reds_t is not an array.
 
On Apr 27, 5:57 pm, "MikeWhy" &lt;boat042-nos...@yahoo.com&gt; wrote:
goous...@googlemail.com&gt; wrote in message

news:11259890.282.1335508094898.JavaMail.geo-discussion-forums@vbvx4...





Am Freitag, 27. April 2012 06:11:25 UTC+2 schrieb MikeWhy:
I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and
some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

    case fsm_state is
        ...
        when reds_t =&gt;           -- illegal, but seems unambiguous enough
            case reds_t'(fsm_state) is
                 when brown =
                     fsm_state &lt;= some_state;

                  when red =
                  when orange =
                     fsm_state &lt;= some_state;

            end case;
        when blues_t'low to blues_t'high =&gt;  -- wordy, but works
           case blues_fsm in
                ...
           end case;
        when invalid =
            ...
    end;

given these declarations:

    type state_t is (
        black, brown, red, orange,
        yellow, green, blue, violet,
        gray, white, invalid
    );
    subtype reds_t   is state_t range brown to orange;
    subtype blues_t  is state_t range green to violet;

    signal fsm_state, some_state : state_t;
    signal blues_fsm : blues_t;

=====
Hi,
reds_t is just a signal name, but not a value, while blues_t'low
represents an actual value.

have you tried what happens when you use

 reds_t'range

??

This is often used in loops like
 for i in my_slv'range loop
to get this interpreted as e.g.
 for i in 31 downto 0 loop

So it might work for the case-when too.

Hi, yes. XST complains that reds_t is not an array.- Hide quoted text -

- Show quoted text -
Click to expand...
Legal vhdl and waht XST will accept is two different things. Did you
try the code in any other, more capable tools (Synplify, modelsim,
etc.)?

Andy
 
Andy wrote:
On Apr 27, 5:57 pm, "MikeWhy" &lt;boat042-nos...@yahoo.com&gt; wrote:
goous...@googlemail.com&gt; wrote in message

news:11259890.282.1335508094898.JavaMail.geo-discussion-forums@vbvx4...


reds_t is just a signal name, but not a value, while blues_t'low
represents an actual value.

have you tried what happens when you use

reds_t'range

??

This is often used in loops like
for i in my_slv'range loop
to get this interpreted as e.g.
for i in 31 downto 0 loop

So it might work for the case-when too.

Hi, yes. XST complains that reds_t is not an array.

Legal vhdl and waht XST will accept is two different things. Did you
try the code in any other, more capable tools (Synplify, modelsim,
etc.)?
Click to expand...
I am limited to the subset that XST will synthesize. Everything else has to
remain hypothetical for the moment. Does synplify accept "case &lt;type_sig&gt; is
when &lt;subtype&gt;'range =&gt;"? No problem with in normal usage; e.g. array type
values in a loop. I just didn't know if it was a tool/language issue, or my
understanding of the language. Hence, the question.
 
Why don't you use the following much simpler description:



case fsm_state is
when brown | red | orange =&gt;
when green | blue | violet =&gt;
when others =&gt;
end case;



Cheers, hssig
 
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