case statements- verilog to vhdl

[FP]

I have the following scenario in verilog which i need to convert to
vhdl

always
if reset
..
..
..
else
case
.
.
.
end case
// set default values
case.
.
.
.
.
end case
end

How do I convert this to vhdl. I am lost on what the equivalent of //
set default values and the case statements after that would be in
VHDL.

 

[jens]

Check out the VHDL Language Reference Guide.

on-line version: http://staffwww.itn.liu.se/~andki/vhdl_refguide/

Windows help version: http://www.iol.ie/~dmurray/Prism/vhdlhlp.zip

 

[Dave Pollum]

On Apr 11, 1:08 pm, FP <FPGA.unkn...@gmail.com> wrote:

I have the following scenario in verilog which i need to convert to
vhdl

always
if reset
.
.
.
else
case
.
.
.
end case
// set default values
case.
.
.
.
.
end case
end

How do I convert this to vhdl. I am lost on what the equivalent of //
set default values and the case statements after that would be in
VHDL.

I'm not a Verilog person, but I do have a book that shows both VHDL
and Verilog code ("HDL Chip Design", by Douglas J. Smiths). The book
shows that "//" is a Verilog comment. So, "// set default values" is
a comment. The Verilog "default" is the same as the VHDL "when others
=>". "always@ .. end" is the same as a VHDL "process .. end
process". In your case (no pun intended), it's a combinatorial
process.
HTH
-Dave Pollum

 

[Andy]

On Apr 11, 2:17 pm, Dave Pollum <vze24...@verizon.net> wrote:

On Apr 11, 1:08 pm, FP <FPGA.unkn...@gmail.com> wrote:



I have the following scenario in verilog which i need to convert to
vhdl

always
if reset
.
.
.
else
case
.
.
.
end case
// set default values
case.
.
.
.
.
end case
end

How do I convert this to vhdl. I am lost on what the equivalent of //
set default values and the case statements after that would be in
VHDL.

I'm not a Verilog person, but I do have a book that shows both VHDL
and Verilog code ("HDL Chip Design", by Douglas J. Smiths). The book
shows that "//" is a Verilog comment. So, "// set default values" is
a comment. The Verilog "default" is the same as the VHDL "when others
=>". "always@ .. end" is the same as a VHDL "process .. end
process". In your case (no pun intended), it's a combinatorial
process.
HTH
-Dave Pollum

The presence of "if reset" could imply that this is a clocked process,
not combinatorial. We can't tell because the "always" statement is not
included, and we cannot tell if the block is also sensitive to posedge
clock.

Andy

 

[Mike Treseler]

FP wrote:

From design point of view I am not sure if I should be putting them in
2 seperate process statements.

No. One verilog block is one vhdl process.

My question is
1) Is the VHDL equivalent of the above, 2 case statements in one
process or 2 different processes with 1 case each?

one process

2) The above is similar to an FSM. One case statement is executing the
present command, while the other is completing the last command. Any
idea on how this should be converted to VHDL?

Did the verilog version work?

-- Mike Treseler

 

[FP]

On Apr 11, 5:18 pm, Andy <jonesa...@comcast.net> wrote:

On Apr 11, 2:17 pm, Dave Pollum <vze24...@verizon.net> wrote:





On Apr 11, 1:08 pm, FP <FPGA.unkn...@gmail.com> wrote:

I have the following scenario in verilog which i need to convert to
vhdl

always
if reset
.
.
.
else
  case
  .
  .
  .
 end case
 // set default values
 case.
 .
 .
 .
 .
end case
end

How do I convert this to vhdl. I am lost on what the equivalent of  //
set default values and the case statements after that would be in
VHDL.

I'm not a Verilog person, but I do have a book that shows both VHDL
and Verilog code ("HDL Chip Design", by Douglas J. Smiths).  The book
shows that "//" is a Verilog comment.  So, "// set default values" is
a comment.  The Verilog "default" is the same as the VHDL "when others
=>".  "always@ .. end" is the same as a VHDL "process .. end
process".  In your case (no pun intended), it's a combinatorial
process.
HTH
-Dave Pollum

The presence of "if reset" could imply that this is a clocked process,
not combinatorial. We can't tell because the "always" statement is not
included, and we cannot tell if the block is also sensitive to posedge
clock.

Andy- Hide quoted text -

- Show quoted text -

I have 2 case statement in 1 always loop in my verilog file. I am not
sure how this should be implemented in VHDL. I am aware of the syntax.
From design point of view I am not sure if I should be putting them in
2 seperate process statements.

Verilog =>

always @ posedge clk
c1 : case(cmd) is
when a => bunch of statements
when b => bunch of statements
when c => bunch of statements
when d => bunch of statements
default => bunch of statements
end case c1

c2 : case(cmd) is
when a => bunch of statements
when b => bunch of statements
when c => bunch of statements
when d => bunch of statements
default => bunch of statements
end case c2

end

My question is
1) Is the VHDL equivalent of the above, 2 case statements in one
process or 2 different processes with 1 case each? The problem with 2
processes I am facing is access of varaibles.
2) The above is similar to an FSM. One case statement is executing the
present command, while the other is completing the last command. Any
idea on how this should be converted to VHDL?

 

[Mike Treseler]

FP wrote:

The verilog code works but I havent deisnged it. So, I am not sure how
its implementation in VHDL woould be.

Unless you post the code, neither am I.

-- Mike Treseler

 

[FP]

On Apr 14, 4:01 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

FP wrote:
From design point of view I am not sure if I should be putting them in
2 seperate process statements.

No. One verilog block is one vhdl process.

My question is
1) Is the VHDL equivalent of the above, 2 case statements in one
process or 2 different processes with 1 case each?

one process

2) The above is similar to an FSM. One case statement is executing the
present command, while the other is completing the last command. Any
idea on how this should be converted to VHDL?

Did the verilog version work?

         -- Mike Treseler

The verilog code works but I havent deisnged it. So, I am not sure how
its implementation in VHDL woould be.