Z
zanzyinlove
Guest
Hello,
WHen we have a condition where we have code like this
case ( a ) // a is a 2 bit number
when "00" : z = b ;
when "01" : z = c ;
when "10" : z = d ;
end case
I understand that if I dont have a default it synthesizes to a latch . But
if we use a "synopsys parallel case" what would it infer ?
if it infers a 3 : 1 mux , what happens if a = "11" ? Does it map to any
other state ? which one?
WHen we have a condition where we have code like this
case ( a ) // a is a 2 bit number
when "00" : z = b ;
when "01" : z = c ;
when "10" : z = d ;
end case
I understand that if I dont have a default it synthesizes to a latch . But
if we use a "synopsys parallel case" what would it infer ?
if it infers a 3 : 1 mux , what happens if a = "11" ? Does it map to any
other state ? which one?