Case choice must be a locally static expression.

[Kenneth Johansson]

Could some language expert explain why adding a constant value to a
constant results in a non constant ?

With base as
constant base : std_logic_vector(7 downto 0) := "10000000"


case addr is

when (base) => -- works

when (base+1) => -- not a static expression HOW??

 

[m]

On Wed, 04 May 2005 17:59:00 +0200, Kenneth Johansson
<kenneth.c.johansson@ericsson.com> wrote:

Could some language expert explain why adding a constant value to a
constant results in a non constant ?

With base as
constant base : std_logic_vector(7 downto 0) := "10000000"


case addr is

when (base) => -- works

when (base+1) => -- not a static expression HOW??

I don't think it's about the constant property of the value but when
the expression would be evaluated. The language allows the delaying of
the evaluation which makes the expression not available when a
constant is needed.

 

[Ben Twijnstra]

Hi Weng,

It is absolutely the fault of software underservice.

Contemporary hardware compilers, especially VHDL compilers, are
inferior to contemporary software compilers not by one level, but by
many levels.

I don't 100% agree with you. Everyday VHDL seems to be a fairly simple
language, but its concurrency and type overloading possibilities make it
hard on the compilers.

It is very clear in your case that 'base' has a contant property, any
binary operator result of one contant with another constant has
constant property.

Not true. What we are looking at here is a non-builtin operation. The
problem is that the '+' operator is actually a function call, namely
ieee.std_logic_arith."+"(std_logic_vector,natural). The compiler is not
allowed to elaborate or execute the call and thus is unable to determine
the resulting value.

Clear?

Best regards,


Ben

 

[Ben Twijnstra]

Hi Weng,

If it is a C or C++, it would have never met the situations. Why? VHDL
is the worst language I have used.It is the language that lacks big
companys' supports and lacks money to introduce more versions of the
language.

You really don't want to know how much money goes around in the EDA world.
And yet another version of the language is not something everything is
waiting for.

As a language, it even doesn't support conditional compilation
statements, like #define, .... Unbelievable. Can you believe any
software language that lacks conditional compilation statements? But
VHDL lives without it and survives.

C does _not_ natively support conditional compilation, inclusion of files or
macros. C++ doesn't either. This functionality is brought to you by cpp,
the C pre-processor.

I use cpp to transform .chd files to .vhd files and then compile these. I
agree that it's a shame that nobody uses this functionality by default, but
it definitely is possible to use it.

In the above case, it is very natural it should have been introduce in
some library all binary operator fucntions, like a "+"
(std_l­ogic_vector_constant,natural). But it lacks
std_l­ogic_vector_constant data type. No body cares about it. Or at
least few people care about it.

Well, if the data type had been a built-in type (integer, natural, bit),
things could have been different, but std_logic and its derivatives are not
native VHDL types, and thus the compiler has to resort to waiting with
evaluating until elaboration time.

It's like creating a "+" function in C++ that adds a number of blank records
to a database. This can't evaluate to a constant either. C++ will give you
very weird results when using this operator in a case statement that will
take you some time to debug. VHDL simply does not allow this kind of stuff.

I don't like VHDL because you have to specify such a large number of data
types explicitly. I like VHDL because it is very literal and avoids side
effects.

Why is C++ so popular? Many big companies open their C++ huge library to
public and public uses them

The thing that makes C++ so popular is that developers don't get into each
others' namespace territories and _should_ not need to care about the
details of lower-level implementations.

In my opinion it's all a bit overrated.

Best regards,


Ben

 

[David R Brooks]

VHDL so *does* support conditional compilation

How about:

if <boolean> generate;
begin
<your code here>
end generate;

"Weng Tianxiang" <wtx@umem.com> wrote:

....
:As a language, it even doesn't support conditional compilation
:statements, like #define, .... Unbelievable. Can you believe any
:software language that lacks conditional compilation statements? But
:VHDL lives without it and survives.
:
....

 

[Kenneth Johansson]

Ben Twijnstra wrote:

Hi Weng,
It is very clear in your case that 'base' has a contant property, any
binary operator result of one contant with another constant has
constant property.


Not true. What we are looking at here is a non-builtin operation. The
problem is that the '+' operator is actually a function call, namely
ieee.std_logic_arith."+"(std_logic_vector,natural). The compiler is not
allowed to elaborate or execute the call and thus is unable to determine
the resulting value.

Clear?

Hmm I have not written vhdl since 97 so I got a bit confused.

But I do not understand why the compiler is not allowed to look inside
the function. The languages has what it called pure functions for
functions whitout sideeffects and that shold be no problem for the
compiler to understand that a pure function called with constant inoput
is going to result in a constant out. Unless the + operatior is
overloaded with a non pure function but why would it be ?

 

[Mike Treseler]

Kenneth Johansson wrote:

Unless the + operatior is
overloaded with a non pure function but why would it be ?

It's not a question of purity, it's a question
of whether the function is built into the standard library.
The function "+" only covers integers in std.standard.
That's just the way it is. You can google for the reasons.
The integer example below compiles fine, for example.

The OP might consider an if/elsif instead of a case
for address decoding.
This will generate no extra logic for non-overlapping
cases and you can use whatever function you like.

-- Mike Treseler
_______________________
entity static is
end entity static;

architecture sim of static is
subtype sel_t is natural range 0 to 255;
constant addr : sel_t := 128;
begin
whatrocess is
subtype sel_t is natural range 0 to 255;
constant addr : sel_t := 42;
constant base : sel_t := 128;
begin
case addr is
when base =>
when base+1 =>
when others =>
end case;
wait;
end process what;
end architecture sim;

 

[Weng Tianxiang]

It is absolutely the fault of software underservice.

Contemporary hardware compilers, especially VHDL compilers, are
inferior to contemporary software compilers not by one level, but by
many levels.

It is very clear in your case that 'base' has a contant property, any
binary operator result of one contant with another constant has
constant property.

You have to bear it.

Weng

 

[Weng Tianxiang]

If it is a C or C++, it would have never met the situations. Why? VHDL
is the worst language I have used.It is the language that lacks big
companys' supports and lacks money to introduce more versions of the
language.

As a language, it even doesn't support conditional compilation
statements, like #define, .... Unbelievable. Can you believe any
software language that lacks conditional compilation statements? But
VHDL lives without it and survives.

In the above case, it is very natural it should have been introduce in
some library all binary operator fucntions, like a "+"
(std_l­ogic_vector_constant,natural). But it lacks
std_l­ogic_vector_constant data type. No body cares about it. Or at
least few people care about it. Why is C++ so popular? Many big
companies open their C++ huge library to public and public uses them

Weng

 

[Weng Tianxiang]

David,
Thank you for your response.

I tried and it works. But it works only for concurrent area and it can
be used for very limited situations.

I have a project using two chips. 80% code of two chips are same. If I
dealt them with two files, it were very difficult to keep them
synchronous.

I finally designed my program to handle the situation and after that
developing and debugging processes go excellent well.

When using C or C++, you never have a feeling that such powerful tools
are available, like C pre-processor. When using VHDL, I really have the
feeling that the VHLD lacks a lot of modern features C and C++
programmers treat them as granted.

For example, this discussion topics asks: why a constant plus a
constant is not a constant? VHDL lacks grease! I know it well and
almost every new comers will ask above similar questions.

It can be resolved very easily from its root:
Add the following segment into VHDL language:

For any data type in VHDL, including all subtypes, if a signal is
defined as a constant, it can be add, subtract, multiple, divide, left
or right shifted by any constant integers and it still has constant
property with its original declared data type. For example, a singal of
two dimention array of std_logic_vector is desclared as a constant, the
signal can be add, ..., by another two dimention array of constants and
it is still a constant of two dimention array of std_logic_vector. You
don't have to add any meanless functions to deal with such general
situations.

Weng