case and parameter in Verilog

[Jonathan Bromley]

On Fri, 18 Sep 2009 03:20:33 -0700 (PDT), Amir wrote:

[presumably inside a "generate"...]

case(inst)
0:
parameter interface_s = "master0.sc";
1:
parameter interface_s = "master1.sc";
endcase

but I get the following Error:
"Not a valid generate item: 'parameter_declaration' [12.1.3(IEEE
2001)]."

do you have any idea why? and how can I solve this?

Why? Because that's what the Verilog-2001 standard says:
you can't declare a parameter or localparam inside a generate.
I think it's fair to say that was an oversight in the
V-2001 standard, and it has been fixed in Verilog-2005
where you CAN declare localparam, but not parameter,
in a generate.

So, the simplest fix is to change "parameter" into "localparam"
and enable Verilog-2005 compilation.

If you can't do that, for whatever reason, then you could
try constructing the parameter *outside* the generate
construct, perhaps like this:

[assuming "inst" is a parameter or localparam...]

// Make the ASCII digit '0' or '1'...
localparam [7:0] inst_digit = "0" + inst;
// Assemble the required string...
localparam interface_s = {"master", inst_digit, ".sc"};

However, if "inst" is a genvar, then you really need
Verilog-2005 to get this right. In -2005 you can use
a genvar as if it were a localparam, but in -2001 that
doesn't quite work right. Steven Sharp will be more
precise on the details than I can be; I wasn't directly
involved in the discussions that led to the -2005
revision.
--
Jonathan Bromley, Consultant

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[Amir]

Hello,
I am trying to write the following code:

case(inst)
0:
parameter interface_s = "master0.sc";
1:
parameter interface_s = "master1.sc";
endcase

but I get the following Error:
"Not a valid generate item: 'parameter_declaration' [12.1.3(IEEE
2001)]."

do you have any idea why? and how can I solve this?

Thanks in advance
-Amir