Cascading of many stages of DCM...

K

Kelvin @ SG

Guest
Hi, group:

I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks
also...
May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or three
DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)?

Will two DCMs cascaded together work well? In one simulation I found the
second DCM
complained the previous stage's skew is greater than 1ns...

How may I do with my situation?

Thanks for your advice.
Kelvin
 
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:buvks6$13g$1@mawar.singnet.com.sg...
Hi, group:

I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks
also...
May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or
three
DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)?

Will two DCMs cascaded together work well? In one simulation I found the
second DCM
complained the previous stage's skew is greater than 1ns...

How may I do with my situation?

Thanks for your advice.
Kelvin
Click to expand...
The biggest problem may be a violation of the DCM's input jitter spec. A
given DCM's output jitter is due to its intrinsic jitter and its input
jitter. I believe that you can safely cascade two, but not three DCM's --
even if the input jitter to the first DCM is zero. You'll have to check the
data sheet and also consider your clock source jitter. If the jitter applied
to a DCM input is too high then it will not lock.

Bob
 
Kelvin @ SG <kelvin8157@hotmail.com> wrote in message
news:buvks6$13g$1@mawar.singnet.com.sg...
Hi, group:
I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks
also...
May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or
three
DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)?
Will two DCMs cascaded together work well? In one simulation I found the
second DCM
complained the previous stage's skew is greater than 1ns...
How may I do with my situation?
Thanks for your advice.
Kelvin
Click to expand...
Kelvin,

You could run all the 36/12/4/1 MHz stuff off the 36 MHz clock
and create clock enables for the 12/4/1 MHz logic. This would
remove any potential problems transferring data between these
different clock domains.

Hope this helps,

Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
 
Yeah, yours is the better approach...However I am converting an ASIC design
into FPGA...
there are a few megabytes of source codes...sigh...that is the problem...




"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message
news:4013975e$0$214$fa0fcedb@lovejoy.zen.co.uk...
Kelvin @ SG <kelvin8157@hotmail.com> wrote in message
news:buvks6$13g$1@mawar.singnet.com.sg...
Hi, group:
I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks
also...
May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or
three
DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)?
Will two DCMs cascaded together work well? In one simulation I found the
second DCM
complained the previous stage's skew is greater than 1ns...
How may I do with my situation?
Thanks for your advice.
Kelvin

Kelvin,

You could run all the 36/12/4/1 MHz stuff off the 36 MHz clock
and create clock enables for the 12/4/1 MHz logic. This would
remove any potential problems transferring data between these
different clock domains.

Hope this helps,

Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
Click to expand...
 
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:bv1hed$8kd$1@mawar.singnet.com.sg...
Yeah, yours is the better approach...However I am converting an ASIC
design
into FPGA...
there are a few megabytes of source codes...sigh...that is the problem...
Click to expand...
If you are familiar with any of the scripting languages you
should be able to write something which looks for the
lower clocks, changes them to the 36Mhz clock and inserts
a pair of lines with the relevant clock enable.

It might be a good idea to get it to display what
it's done and get you to confirm it, or add comments
above every changed line with an easily found search
string so you can quickly check what it's done.

Give it a _thorough_ visial inspection and make sure
it's _well_ simulated to check you haven't messed up.

Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
 
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