M
Morten Leikvoll
Guest
I do a rather heavy cascaded clock division/multiplication using DLL's in a
VirtexE and have problems with routing resources from/to the dll's.
I do not have enough resources to route all LOCKED signals through an
inverter (and delay for 2x feedback's) and therefore do a delayed reset from
one to the next. My question is:How much delay do I need to be sure that the
output of one DLL is locked before I reset the next one? Does anyone have
experience with this?
VirtexE and have problems with routing resources from/to the dll's.
I do not have enough resources to route all LOCKED signals through an
inverter (and delay for 2x feedback's) and therefore do a delayed reset from
one to the next. My question is:How much delay do I need to be sure that the
output of one DLL is locked before I reset the next one? Does anyone have
experience with this?