cascaded dividers for dividing down clocks

[anand]

Hi

I have observed in our past 2-3 designs that dividers (for PLL/Post and
Pre dividers to generate clocks of different frequencies) are almost
always in cascaded form.
is there a specific reason why this is designed this way? Why not have
a singe stage divider instead of 3 stages?

 

[gabor]

anand wrote:

Hi

I have observed in our past 2-3 designs that dividers (for PLL/Post and
Pre dividers to generate clocks of different frequencies) are almost
always in cascaded form.
is there a specific reason why this is designed this way? Why not have
a singe stage divider instead of 3 stages?

What technology are you using? The most comman reason to
cascade dividers is that a longer divider won't meet the carry
chain timing at the input frequency. The first stage in this case
is normally referred to as a prescaler. A long synchronous
counter needs to meet the carry in to the last flip-flop within
1 clock cycle. A ripple-carry counter can run at the toggle
rate of the first flip-flop.

HTH,
Gabor