carry look-ahead adder

[khushalgelda]

i connected 2 4-bit carry look-ahead adders. everything worked fine
but i dont see COUT2 in my simulation window..
whats the problem ??


// 1st cla
module alu1(cout,sum,x,y,cin);
output cout;
output [3:0] sum;
input [3:0] x,y;
input cin;
wire [3:0] g,p;
wire [4:0] c;
assign c[0] = cin;
assign g[3:0] = x[3:0] & y[3:0];
assign p[3:0] = x[3:0] ^ y[3:0];

assign c[1] = g[0] | (p[0]&cin);
assign c[2] = g[1] | (p[1]&g[0]) | (p[1]&p[0]&cin);
assign c[3] = g[2] | (p[2]&g[1]) | (p[2]&p[1]&g[0]) |
(p[2]&p[1]&p[0]&cin);
assign c[4] = g[3] | (p[3]&g[2]) | (p[3]&p[2]&g[1]) |
(p[3]&p[2]&p[1]&g[0]) | (p[3]&p[2]&p[1]&p[0]&cin);
assign sum[3:0] = p[3:0] ^ c[3:0];
assign cout=c[4];

endmodule

// 2nd cla
module alu2(cout2,sum,x,y,cout);
output wire cout2;
output [7:4] sum;
input [7:4] x,y;
input cout;
wire [7:4] g,p;
wire [8:4] c;
assign c[4] = cout;
assign g[7:4] = x[7:4] & y[7:4];
assign p[7:4] = x[7:4] ^ y[7:4];

assign c[5] = g[4] | (p[4]&cout);
assign c[6] = g[5] | (p[5]&g[4]) | (p[5]&p[4]&cout);
assign c[7] = g[6] | (p[6]&g[5]) | (p[6]&p[5]&g[4]) |
(p[6]&p[5]&p[4]&cout);
assign c[8] = g[7] | (p[7]&g[6]) | (p[7]&p[6]&g[5]) |
(p[7]&p[6]&p[5]&g[4]) | (p[7]&p[6]&p[5]&p[4]&cout);
assign sum[7:4] = p[7:4] ^ c[7:4];
assign cout2=c[8];
endmodule

// joining 2 4-bit carry look-ahead adders
module top(COUT2, SUM, X,Y,CIN);
output COUT2;
input [7:0] X,Y;
input CIN;
output [7:0] SUM;
wire cout;
// instantiating
alu1 alu1(cout,SUM[3:0],X[3:0],Y[3:0],CIN);
alu2 alu2(COUT2,SUM[7:4],X[7:4],Y[7:4],cout);
endmodule

 

[John_H]

On Aug 26, 4:24 pm, khushalgelda <khushalge...@gmail.com> wrote:

i connected 2 4-bit carry look-ahead adders. everything worked fine
but i dont see COUT2 in my simulation window..

First, an observation: are you aware that the two ALU modules are the
same and you could implement the second ALU as alu1
alu2(COUT,SUM[7:4],X[7:4],Y[7:4],cout); ?

The idea behind using modules is so that you can instantiate them
without having a preconception of what the individual wires are for
multiple instances - like two ALUs chained together.

You may simply be having simulation problems since I don't see any of
the "usual suspects" in your code.

Do you see the cout in your simulation?

Do you see the SUM in your simulation?

perhaps you can get to where you want to be without too much
difficulty. Especially when using a simulator, tracking down a
problem is pretty straight forward with a divide and conquer approach:
if you can see what goes into a small black and what comes out is bad,
chop the block up into smaller pieces and see if those work or if they
don't. You eventually get to the tiniest tidbit that's causing the
problem. Zero in. Find it.

 

[khushalgelda]

On Aug 30, 6:10 am, John_H <newsgr...@johnhandwork.com> wrote:

On Aug 26, 4:24 pm, khushalgelda <khushalge...@gmail.com> wrote:

i connected 2 4-bit carry look-ahead adders. everything worked fine
but i dont see COUT2 in my simulation window..

First, an observation: are you aware that the two ALU modules are the
same and you could implement the second ALU as alu1
alu2(COUT,SUM[7:4],X[7:4],Y[7:4],cout); ?

The idea behind using modules is so that you can instantiate them
without having a preconception of what the individual wires are for
multiple instances - like two ALUs chained together.

You may simply be having simulation problems since I don't see any of
the "usual suspects" in your code.

Do you see the cout in your simulation?

Do you see the SUM in your simulation?

perhaps you can get to where you want to be without too much
difficulty.  Especially when using a simulator, tracking down a
problem is pretty straight forward with a divide and conquer approach:
if you can see what goes into a small black and what comes out is bad,
chop the block up into smaller pieces and see if those work or if they
don't.  You eventually get to the tiniest tidbit that's causing the
problem.  Zero in.  Find it.

I get your point... actually that was my first verilog code so i dint
eactly know how to use it..
but now i am clear wid it. thnk