Carbon nanotubes

  • Thread starter Martin Euredjian
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Martin Euredjian

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A good article in the latest IEEE Spectrum. Probably a ways out, but I'll
ask. Any work/thoughts on this technology applied to FPGA's?


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Martin Euredjian

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Martin Euredjian wrote:
A good article in the latest IEEE Spectrum. Probably a ways out, but I'll
ask. Any work/thoughts on this technology applied to FPGA's?
I'm not so sure it is "a ways out". Lasts weeks EE Times had a good
article about several IP vendors and one will have product this year.
"Cavendish Kinetics is introducing its cantilevered-beam approach this
year initially for electroic fuse components in analog and mixed-signal
circuits. That will be followed by a one-tim-programmable memory for
embedded applications and then a many-times-programmable variety."

I would expect this would make a great FPGA configuration memory
technology. It is 10 times smaller than an SRAM cell, not affected by
alpha particles (the article did not say about higher energy radiation)
and non-volitile. They don't say what size CMOS process they are
working with, but they indicate it should be scalable down to 22 nm.

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Rick "rickman" Collins

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Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
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Cavendish Kinetics is introducing its cantilevered-beam approach
I emailed them today. I'll be in Amsterdam next month and might have an
opportunity to visit. Sounds interesting.


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Martin Euredjian

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