capacitor placement

[rob d]

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

 

On Wednesday, 25 September 2019 10:34:19 UTC+1, rob d wrote:

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

It is worth thinking about why it could matter where the capacitor
is placed. There will almost certainly be some impedance mismatch
at the transmitter end of the transmission line. The receiver end
is more likely to be accurately terminated. In such a situation,
there will be negligible reflection at the receiver and the signals
will be clean. If you add a capacitor this may cause a mismatch
due to its large size relative to the signal tracks and there will
be some reflection from it. There could be multiple reflections
between the source mismatch and the capacitor mismatch leading to
variations in the frequency response of the transmission line.

In extreme cases this looks like a comb filter. By keeping the
capacitor close to the source mismatch the frequency of the first
null or dip is kept as high as possible, hopefully above the
system operating range.

If you can't achieve this, then try to make the capacitor match
as good as possible by using the smallest possible package size,
preferably one where the width of the capacitor is similar to the
track width.

John

 

On Wed, 25 Sep 2019 02:34:14 -0700 (PDT), rob d <rjd4567@gmail.com>
wrote:

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

If they are DC blocks in the signal path, on an impedance-matched
trace or pair, it doesn't matter where they are.

 

[John Larkin]

On Wed, 25 Sep 2019 11:01:56 -0700 (PDT), jrwalliker@gmail.com wrote:

On Wednesday, 25 September 2019 15:10:02 UTC+1, jla...@highlandsniptechnology.com wrote:
On Wed, 25 Sep 2019 02:34:14 -0700 (PDT), rob d <rjd4567@gmail.com
wrote:

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

If they are DC blocks in the signal path, on an impedance-matched
trace or pair, it doesn't matter where they are.

True, but if one end is better matched than the other then it can
make a difference (which may or may not be important).

John

How?

 

On Wednesday, 25 September 2019 15:10:02 UTC+1, jla...@highlandsniptechnology.com wrote:

On Wed, 25 Sep 2019 02:34:14 -0700 (PDT), rob d <rjd4567@gmail.com
wrote:

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

If they are DC blocks in the signal path, on an impedance-matched
trace or pair, it doesn't matter where they are.

True, but if one end is better matched than the other then it can
make a difference (which may or may not be important).

John

 

On Wednesday, 25 September 2019 19:41:45 UTC+1, John Larkin wrote:

On Wed, 25 Sep 2019 11:01:56 -0700 (PDT), jrwalliker@gmail.com wrote:

On Wednesday, 25 September 2019 15:10:02 UTC+1, jla...@highlandsniptechnology.com wrote:
On Wed, 25 Sep 2019 02:34:14 -0700 (PDT), rob d <rjd4567@gmail.com
wrote:

Hi all.

I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

Am I missing something, or can anyone suggest a manager friendly document to help my argument.

Rob

If they are DC blocks in the signal path, on an impedance-matched
trace or pair, it doesn't matter where they are.

True, but if one end is better matched than the other then it can
make a difference (which may or may not be important).

John

How?

If the transmitter circuit is mismatched and the receiver is well
matched and the capacitor introduces a mismatch there can be
multiple reflections between the transmitter and the capacitor.
This will introduce nulls in the frequency response of the
transmission line at frequencies depending on the spacing between
the driver circuit and the capacitor. The equivalent in optics is
the Fabry Perot interferometer.

If the capacitor is well matched to the transmission line then
of course its position doesn't matter. With the very small
capacitors now available this may well be the case. Also,
with FR4 at around 10GHz the losses may damp any resonances
enough that they become unimportant.

John


John