Capacitor Issue

[hillbrk@auburn.edu]

Has anyone used a capacitor in layout? If so, is there any way that the
lvs will pass recognizing the cap in both the schmatic and layout?

Thanks

 

[hillbrk@auburn.edu]

I am using AMIS C5 process

 

[Andrew Beckett]

On 7 Apr 2006 07:33:51 -0700, "hillbrk@auburn.edu" <hillbrk@auburn.edu> wrote:

Has anyone used a capacitor in layout? If so, is there any way that the
lvs will pass recognizing the cap in both the schmatic and layout?

Thanks

What a ridiculous question!

Of course people have used capacitors in layout, and of course LVS can pass with
capacitors in schematic and layout.

Presumably you have a specific problem.

You should realise that unless you post a reasonable question, with sufficient
details, you cannot expect to get a reasonable answer.

Regards,

Andrew.

 

[fogh]

Andrew Beckett wrote:

On 7 Apr 2006 07:33:51 -0700, "hillbrk@auburn.edu" <hillbrk@auburn.edu> wrote:


Has anyone used a capacitor in layout? If so, is there any way that the
lvs will pass recognizing the cap in both the schmatic and layout?

Thanks


What a ridiculous question!

Of course people have used capacitors in layout, and of course LVS can pass with
capacitors in schematic and layout.

Presumably you have a specific problem.

You should realise that unless you post a reasonable question, with sufficient
details, you cannot expect to get a reasonable answer.

Andrew,

agree on the lack of details. But... he gives already the details
about the process/pdk and you would (still, maybe) be amazed how many
obvious flow errors make it in a final pdk that is allegedly used all
over the world and been around.