Can't program Spartan3A with JTAG

A

aleksa

Guest
Impact reports something like "device not recognized" and then I point
it to the .bit file.
Reading ID / signature shows that all bits are zeros.

Using the scope I can see that all signals (TMS, TCK, TDI, TDO) change
states.
I have an old analog scope and the time period is very short (for me,
human),
but I can see that signals are valid (0 and 3V3, nothing strange
happening).

Can I make Impact talk to the fpga more often, so I can better see the
signals?
(If not, I could make a prog to toggle the port pins...)

I've used the same JTAG programming board for Spartan 2, and it works.
Spartan2, Spartan3A and parallel port JTAG boards were all done by me.

I have the PROG pin HIGH, the rest are floating.
Then I've connected M0-M2 and PUDC HIGH, but its the same.

Any thoughts?
 
On Jan 30, 10:06 pm, aleksa <aleks...@gmail.com> wrote:

the rest are floating.
Click to expand...
i.e. CCLK, DIN, CS, INIT, all clocks.
Power pins are connected :)
 
On Jan 30, 1:06 pm, aleksa <aleks...@gmail.com> wrote:
Impact reports something like "device not recognized" and then I point
it to the .bit file.
Reading ID / signature shows that all bits are zeros.

Using the scope I can see that all signals (TMS, TCK, TDI, TDO) change
states.
I have an old analog scope and the time period is very short (for me,
human),
but I can see that signals are valid (0 and 3V3, nothing strange
happening).

Can I make Impact talk to the fpga more often, so I can better see the
signals?
(If not, I could make a prog to toggle the port pins...)

I've used the same JTAG programming board for Spartan 2, and it works.
Spartan2, Spartan3A and parallel port JTAG boards were all done by me.

I have the PROG pin HIGH, the rest are floating.
Then I've connected M0-M2 and PUDC HIGH, but its the same.

Any thoughts?
Click to expand...
Having the IDCODE reported as all zeros indicates that the JTAG is
broken somewhere or the TAP controller is being held in reset.

1) You indicated the PROGRAM_B was high (was this measured?), but what
about INIT_B?
2) Have you confirm that TCK is getting to the TCK pin of the
Spartan-3A device?
3) Have you probed the TDO at the Spartan-3A device for any activity?

Ed McGettigan
--
Xilinx Inc.
 
On Jan 30, 11:31 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Jan 30, 1:06 pm, aleksa <aleks...@gmail.com> wrote:





Impact reports something like "device not recognized" and then I point
it to the .bit file.
Reading ID / signature shows that all bits are zeros.

Using the scope I can see that all signals (TMS, TCK, TDI, TDO) change
states.
I have an old analog scope and the time period is very short (for me,
human),
but I can see that signals are valid (0 and 3V3, nothing strange
happening).

Can I make Impact talk to the fpga more often, so I can better see the
signals?
(If not, I could make a prog to toggle the port pins...)

I've used the same JTAG programming board for Spartan 2, and it works.
Spartan2, Spartan3A and parallel port JTAG boards were all done by me.

I have the PROG pin HIGH, the rest are floating.
Then I've connected M0-M2 and PUDC HIGH, but its the same.

Any thoughts?

Having the IDCODE reported as all zeros indicates that the JTAG is
broken somewhere or the TAP controller is being held in reset.

1) You indicated the PROGRAM_B was high (was this measured?), but what
about INIT_B?
2) Have you confirm that TCK is getting to the TCK pin of the
Spartan-3A device?
3) Have you probed the TDO at the Spartan-3A device for any activity?

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Yes, PROG is HIGH.
INIT_B was floating. I've pulled it up now, but no change.

TDO does show activity.

I've made a prog to pulse (500 kHz) the TMS, TCK and TDI signals,
and they all get to FPGA, nice and clean.
 
some tests I did:

1. started iMPACT.
2. double click on Boundary scan.
3. right click, Initialize Chain.

I get blue text "Identify succeeded"
The part is already shown as unknown.

I'm asked "Do you want to cont. and assign conf. files?" YES
"Do you have a BSDL or BIT file?" YES (xc3s50a.bsd)

4. Debug, Chain integrity test = OK.

Everything else fails.
 
On Jan 31, 4:46 am, aleksa <aleks...@gmail.com> wrote:
some tests I did:

1. started iMPACT.
2. double click on Boundary scan.
3. right click, Initialize Chain.

I get blue text "Identify succeeded"
The part is already shown as unknown.

I'm asked "Do you want to cont. and assign conf. files?" YES
"Do you have a BSDL or BIT file?" YES (xc3s50a.bsd)

4. Debug, Chain integrity test = OK.

Everything else fails.
Click to expand...
What was the IDCODE reported by iMPACT?
When you put the oscilloscope on the TDO output what voltage levels
did you see?
Is the TDO of the part connected to the TDO of the cable?
Are there any other devices in the JTAG chain?

Ed McGettigan
--
Xilinx Inc.
 
On Jan 31, 4:25 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Jan 31, 4:46 am, aleksa <aleks...@gmail.com> wrote:

some tests I did:

1. started iMPACT.
2. double click on Boundary scan.
3. right click, Initialize Chain.

I get blue text "Identify succeeded"
The part is already shown as unknown.

I'm asked "Do you want to cont. and assign conf. files?" YES
"Do you have a BSDL or BIT file?" YES (xc3s50a.bsd)

4. Debug, Chain integrity test = OK.

Everything else fails.

What was the IDCODE reported by iMPACT?
Click to expand...
IDCODE = all zeros


When you put the oscilloscope on the TDO output what voltage levels
did you see?
Click to expand...
0 and 3.2V


Is the TDO of the part connected to the TDO of the cable?
Click to expand...
Yes, I've placed a JTAG gif here
http://www60.zippyshare.com/v/18748688/file.html


Are there any other devices in the JTAG chain?
Click to expand...
No
 
On Jan 31, 7:44 am, aleksa <aleks...@gmail.com> wrote:
On Jan 31, 4:25 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Jan 31, 4:46 am, aleksa <aleks...@gmail.com> wrote:

some tests I did:

1. started iMPACT.
2. double click on Boundary scan.
3. right click, Initialize Chain.

I get blue text "Identify succeeded"
The part is already shown as unknown.

I'm asked "Do you want to cont. and assign conf. files?" YES
"Do you have a BSDL or BIT file?" YES (xc3s50a.bsd)

4. Debug, Chain integrity test = OK.

Everything else fails.

What was the IDCODE reported by iMPACT?

IDCODE = all zeros

When you put the oscilloscope on the TDO output what voltage levels
did you see?

0 and 3.2V

Is the TDO of the part connected to the TDO of the cable?

Yes, I've placed a JTAG gif herehttp://www60.zippyshare.com/v/18748688/file.html

Are there any other devices in the JTAG chain?

No- Hide quoted text -

- Show quoted text -
Click to expand...
Ok, so the TDO is outputing a waveform in the right range of 0 to
3.2V, but the not showing up in the impact software. This means that
the problem is in your custom cable.

I can't tell exactly how the cable was constructed from the circuit
that you posted as the part numbers are not complete and there are no
VCC connections of any type. Have you put a scope on the TDO output
of the "LVC25" and the "HCT08" devices?

Ed McGettigan
--
Xilinx Inc.
 
On 01/30/2011 03:06 PM, aleksa wrote:

I've used the same JTAG programming board for Spartan 2, and it works.
Spartan2, Spartan3A and parallel port JTAG boards were all done by me.
Have you tested this cable with the Spartan 2 TODAY? I have blown out
Click to expand...
my parallel programming pod several times from ESD and bad power outlet
grounds on a couple occasions.

Jon
 
On Jan 31, 9:11 pm, Jon Elson <jmel...@wustl.edu> wrote:
On 01/30/2011 03:06 PM, aleksa wrote:

I've used the same JTAG programming board for Spartan 2, and it works.
Spartan2, Spartan3A and parallel port JTAG boards were all done by me.

Have you tested this cable with the Spartan 2 TODAY?  I have blown out
my parallel programming pod several times from ESD and bad power outlet
grounds on a couple occasions.

Jon
Click to expand...
I just did that, and everything works.
For example, IDCODE is '10000000011000010000000010010011'
(XC2S50 TQG144)
 
On Jan 31, 7:27 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Jan 31, 7:44 am, aleksa <aleks...@gmail.com> wrote:





On Jan 31, 4:25 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Jan 31, 4:46 am, aleksa <aleks...@gmail.com> wrote:

some tests I did:

1. started iMPACT.
2. double click on Boundary scan.
3. right click, Initialize Chain.

I get blue text "Identify succeeded"
The part is already shown as unknown.

I'm asked "Do you want to cont. and assign conf. files?" YES
"Do you have a BSDL or BIT file?" YES (xc3s50a.bsd)

4. Debug, Chain integrity test = OK.

Everything else fails.

What was the IDCODE reported by iMPACT?

IDCODE = all zeros

When you put the oscilloscope on the TDO output what voltage levels
did you see?

0 and 3.2V

Is the TDO of the part connected to the TDO of the cable?

Yes, I've placed a JTAG gif herehttp://www60.zippyshare.com/v/18748688/file.html

Are there any other devices in the JTAG chain?

No- Hide quoted text -

- Show quoted text -

Ok, so the TDO is outputing a waveform in the right range of 0 to
3.2V, but the not showing up in the impact software.  This means that
the problem is in your custom cable.

I can't tell exactly how the cable was constructed from the circuit
that you posted as the part numbers are not complete and there are no
VCC connections of any type.  Have you put a scope on the TDO output
of the "LVC25" and the "HCT08" devices?

Ed McGettigan
--
Xilinx Inc.
Click to expand...
LVC125 is powered by 3V3.
HCT08 by 5V (to comply with the parallel port)

No, I didn't put the scope directly on HCT08,
but that must work, since I just tested it again
with Spartan 2. Looks like something on my Spartan 3A
board is wrong, but don't know what.

Here is the sch of Spartan 3A board:
http://www41.zippyshare.com/v/38225858/file.html

notes:

X1 and U2 are not populated.

pins not shown on FPGA are GND pins.

S1, S2 and S3 are the connecting cable to parallel JTAG prog.

Currently, PUDC(99), CS(46) and INIT(48) are pulled to 3V3.
(I've soldered 3 extra resistors). PROG has R9 already.

M0, M1, M2, DONE, CCLK, DIN and all GCKS are floating.

As for the rest of the plain I/O pins:
some are floating, some are connected to 3V3 micro.
 
I should add that S1 and S2 are two-pin connectors,
but have five wires: two signals and three GNDs,
which are cut just above the connector.
 
On Jan 31, 2:17 pm, aleksa <aleks...@gmail.com> wrote:
I should add that S1 and S2 are two-pin connectors,
but have five wires: two signals and three GNDs,
which are cut just above the connector.
Click to expand...
Two pin connectors, but five wires??? Could you have a short in this
bundle?

You should still check the LVC25 and HCT08 connections to see if the
TDO signal is getting through.

Ed McGettigan
--
Xilinx Inc.
 
You need to probe TDI,TMS and TCK as close to the FPGA pins as possible, and
TDO at the parallel port.
Are you able to grab a full IDCODE read with all signals on a 4ch scope or
logic analyzer? I'd like to see that image.
 
On Feb 1, 9:03 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
You need to probe TDI,TMS and TCK as close to the FPGA pins as possible, and
TDO at the parallel port.
Are you able to grab a full IDCODE read with all signals on a 4ch scope or
logic analyzer? I'd like to see that image.
Click to expand...
OK, I have it working now.

I had series res on JTAG side, but not on the FPGA side.
I've added them (330E) on all signals, and it works now.

Here is the photo of the TMS on scope:
http://www23.zippyshare.com/v/50101972/file.html
before/after means before/after adding series res on FPGA.

Before, LOW level was 0.2V, now is 0.4V.
I'll fix that later. And will also use smaller R.

The photo is of the TMS. TDI and TCK are similar.
TDO I still didn't check, because its not easy to
put a probe on a comp below desk.

Anyway, signal integrity will be the first thing to
check from now on, regardless whether it works
on Spartan 2 or not :)
 
"aleksa" <aleksazr@gmail.com> wrote in message
news:99e0701d-1068-4416-b18a-a19ed7aa5166@x5g2000prf.googlegroups.com...
Thanks everyone
Click to expand...
Just to close up, the res is probably only needed on the TCK to avoid
"ringing" wich may be detected as multiple clocks at the edges. It is caused
by bad impedance match on the transmission line. The problem the res can add
is lower max programming speed because of slower rise/fall times, but
usually the speed is not near the problem area on such parallel devices.
 
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