Can't migrate from 11.5 to 12.3

[ghelbig]

Normally I would contact Xilinx directly, but my FAE's email just
bounced.



I have a design that works in 11.5, and does not work in 12.3.

It's not meeting timing in 11.5 due to routing delays (the top 5
timing offenders are all > 80% route), so I tried it in 12.3.

First pass MAP failed. It told me to add constraints to get it to
build. When I add the constraints, PAR reports un-routable nets.

This from the usage of the GTX_DUAL module in a Virtex-5

Any ideas? What files would be interesting?

 

[MM]

First, make sure you clean the project well. What was the original MAP
error? Was it related to enabling idle GTX tiles for passing reference
clock?

/Mikhail



"ghelbig" <ghelbig@lycos.com> wrote in message
news:2dfc4e04-88d0-41df-a9b5-85c9350a302e@s9g2000vby.googlegroups.com...

Normally I would contact Xilinx directly, but my FAE's email just
bounced.



I have a design that works in 11.5, and does not work in 12.3.

It's not meeting timing in 11.5 due to routing delays (the top 5
timing offenders are all > 80% route), so I tried it in 12.3.

First pass MAP failed. It told me to add constraints to get it to
build. When I add the constraints, PAR reports un-routable nets.

This from the usage of the GTX_DUAL module in a Virtex-5

Any ideas? What files would be interesting?

 

[ghelbig]

On Oct 29, 11:05 am, "MM" <mb...@yahoo.com> wrote:

First, make sure you clean the project well. What was the original MAP
error? Was it related to enabling idle GTX tiles for passing reference
clock?

/Mikhail

I keep all the ISE files in a separate directory. For this migration,
I copied the xise file from .../ise to .../ise.123 - just the xise and
the ucf file. Then I let ISE have its way with the directory - I'm
pretty sure this starts with a clean project.

The map error message is:

ERRORlace:1040 - Unroutable Placement! An IPAD / GT component pair
have been found that are not placed at a routable
IPAD / GT site pair. The IPAD component <RX3_P> is placed at site
<IPAD_X1Y25>. The corresponding GT component
<MGT_RX3_RF/GTX_DUAL_DNA> is placed at site <GTX_DUAL_X0Y0>. The
IPAD can route to the GT <RXP0> pin only if the load
component is placed at an offset of (-2, -2) with respect to the
driver component. This placement is UNROUTABLE in
PAR and therefore, this error condition should be fixed in your
design. You may use the CLOCK_DEDICATED_ROUTE
constraint in the .ucf file to demote this message to a WARNING in
order to generate an NCD file. This NCD file can
then be used in FPGA Editor to debug the problem. A list of all the
COMP.PINS used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file
to demote this ERROR to a WARNING.

The only placement constraint I have created is the pin number.

Gary.

 

[Ed McGettigan]

On Oct 29, 12:25 pm, ghelbig <ghel...@lycos.com> wrote:

On Oct 29, 11:05 am, "MM" <mb...@yahoo.com> wrote:

First, make sure you clean the project well. What was the original MAP
error? Was it related to enabling idle GTX tiles for passing reference
clock?

/Mikhail

I keep all the ISE files in a separate directory.  For this migration,
I copied the xise file from .../ise to .../ise.123 - just the xise and
the ucf file.  Then I let ISE have its way with the directory - I'm
pretty sure this starts with a clean project.

The map error message is:

ERRORlace:1040 - Unroutable Placement! An IPAD / GT component pair
have been found that are not placed at a routable
   IPAD / GT site pair. The IPAD component <RX3_P> is placed at site
IPAD_X1Y25>. The corresponding GT component
   <MGT_RX3_RF/GTX_DUAL_DNA> is placed at site <GTX_DUAL_X0Y0>. The
IPAD can route to the GT <RXP0> pin only if the load
   component is placed at an offset of (-2, -2) with respect to the
driver component. This placement is UNROUTABLE in
   PAR and therefore, this error condition should be fixed in your
design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in
order to generate an NCD file. This NCD file can
   then be used in FPGA Editor to debug the problem. A list of all the
COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file
to demote this ERROR to a WARNING.

The only placement constraint I have created is the pin number.

Gary.

If you constraining both the GTX instance and the TX/RX ports change
to just constraining the GTX instance and the software will place the
TX/RX ports in the one and only place that it can.

Ed McGettigan
--
Xilinx Inc.

 

[ghelbig]

On Oct 29, 1:28 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

The only placement constraint I have created is the pin number.

Gary.

If you constraining both the GTX instance and the TX/RX ports change
to just constraining the GTX instance and the software will place the
TX/RX ports in the one and only place that it can.

Ed McGettigan
--
Xilinx Inc.- Hide quoted text -

- Show quoted text -

"The only placement constraint I have created is the pin number."

It fails in MAP, before the GTX instance is placed. Unless I'm
totally confused about how a GTX instance is constrained.

Gary.

 

[Ed McGettigan]

On Oct 29, 4:16 pm, ghelbig <ghel...@lycos.com> wrote:

On Oct 29, 1:28 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:



The only placement constraint I have created is the pin number.

Gary.

If you constraining both the GTX instance and the TX/RX ports change
to just constraining the GTX instance and the software will place the
TX/RX ports in the one and only place that it can.

Ed McGettigan
--
Xilinx Inc.- Hide quoted text -

- Show quoted text -

"The only placement constraint I have created is the pin number."

It fails in MAP, before the GTX instance is placed.  Unless I'm
totally confused about how a GTX instance is constrained.

Gary.

The error message says that the GTX is placed at site GTX_DUAL_X0Y0
and that it can't route the RXP0 pin to the site IPAD_X1Y25. You
didn't say what part/package combo this is so I can't determine what
the cause is. It could be that you used the RXP1 location in your
constraints instead of RXP0.

Ed McGettigan
--
Xilinx Inc.