Can't identify type of gate in diagram explaining inner work

[John Albers]

There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters. If
it is a straight OR gate, then I don't understand how the circuit
would work because pin 4 is always held high and this would force the
Rst to always be high also. If the little circles are invertors, then
I don't understand why both of them need to be there. I am also
assuming that the flip flop is the traditional RS flip flop.

Any help would be greatly appreciated.

Thank You

 

[Sir Charles W. Shults III]

Check out DeMorgan's Theorem. If you invert the inputs of a gate, it
changes families and polarities. An OR gate becomes a NAND. Does that help
you any?

Cheers!

Chip Shults

 

[John Popelish]

John Albers wrote:

There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters. If
it is a straight OR gate, then I don't understand how the circuit
would work because pin 4 is always held high and this would force the
Rst to always be high also. If the little circles are invertors, then
I don't understand why both of them need to be there.

Yes, the gate is an or gate with inverters on both its input. So the
output goes high (true) if either input goes low.

I am also
assuming that the flip flop is the traditional RS flip flop.

Yes.

Any help would be greatly appreciated.

Thank You

--
John Popelish

 

[Thaas]

On 28 Apr 2004 06:19:00 -0700, jalbers@bsu.edu (John Albers) wrote:

There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters. If
it is a straight OR gate, then I don't understand how the circuit
would work because pin 4 is always held high and this would force the
Rst to always be high also. If the little circles are invertors, then
I don't understand why both of them need to be there. I am also
assuming that the flip flop is the traditional RS flip flop.

Any help would be greatly appreciated.

Thank You

John,

When an OR gate is drawn with bubbled inputs it is actually a NAND
gate. The representations are equivalent per De Morgan's theorem.

When drawn as a bubbled OR gate the equation for inputs A & B with
output C reads: NOT-A OR NOT-B = C. Drawn as a NAND the equation
reads A AND B = NOT-C. The truth tables for these equations are of
course identical.

In other words drawing the circuit with a bubbled OR is saying "Either
A or B low will cause a reset." Drawing it as a NAND would say " A
and B must both be high to prevent a reset."

--
Thaas

 

[John Popelish]

Soeren wrote:

Hi John,

Yes, the gate is an or gate with inverters on both its input. So the
output goes high (true) if either input goes low.

But unfortunately it is a drawing error, the 555 does not work that way.

Internally, the functions are implemented differently, but from a
black box perspective, I think this is a functional description.
Please elaborate on how this model is wrong.

--
John Popelish

 

[grahamk]

Soeren wrote:

Hi John,


There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

Take a look at Tonys 555-tutor:
URL:http://www.uoguelph.ca/~antoon/gadgets/555/555.html

And/or (or should it be nand/nor get the datasheet for ICM7555 from
Philips (page 2 has a nice drawing which should help you).


However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters.

Actually, it is a drawing_error_gate

Have a look at


http://homepage.ntlworld.com/g.knott/elect388.htm

 

[Soeren]

Hi John,

Yes, the gate is an or gate with inverters on both its input. So the
output goes high (true) if either input goes low.

But unfortunately it is a drawing error, the 555 does not work that way.


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *

 

[Soeren]

Hi John,

There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

Take a look at Tonys 555-tutor:
<URL:http://www.uoguelph.ca/~antoon/gadgets/555/555.html>

And/or (or should it be nand/nor get the datasheet for ICM7555 from
Philips (page 2 has a nice drawing which should help you).

However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters.

Actually, it is a drawing_error_gate


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *

 

[Soeren]

Hi John,

Internally, the functions are implemented differently,

Yup, but that is not what I am referring to.

but from a
black box perspective, I think this is a functional description.
Please elaborate on how this model is wrong.

To reset the output of the 555, either the reset pin (4) must be "low"
*OR* the voltage on the threshold pin must be above 2/3 Vcc.

The "threshold comparator" output is "high" when the threshold pin (6)
is above 2/3 Vcc.

From this follows, that the NAND gate (OR w. inverted inputs) cannot
work, which is probably what confused John Albers.

Remove the topmost inverter-bubble on the OR gate and I will find the
description functional


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *

 

[John Popelish]

Soeren wrote:

Hi John,

Internally, the functions are implemented differently,

Yup, but that is not what I am referring to.

but from a
black box perspective, I think this is a functional description.
Please elaborate on how this model is wrong.

To reset the output of the 555, either the reset pin (4) must be "low"
*OR* the voltage on the threshold pin must be above 2/3 Vcc.

The "threshold comparator" output is "high" when the threshold pin (6)
is above 2/3 Vcc.

From this follows, that the NAND gate (OR w. inverted inputs) cannot
work, which is probably what confused John Albers.

Remove the topmost inverter-bubble on the OR gate and I will find the
description functional

The comparator shown for the threshold input is connected as
inverting, so that a high input will produce a low on the input of the
gate.

According to the approximate internal schematic shown on page 1 of:
http://www.national.com/ds/LM/LM555.pdf
if you consider Q17 to be the output of the threshold comparator, this
comparator is connected to invert the polarity of the threshold
input. Its collector or Q17 is wire ORed (negative active ORed) with
the signal from the reset emitter follower to reset the flip flop when
either pulls low. So the model is usably accurate as far as I can
tell.

--
John Popelish

 

[Soeren]

Hi Graham,

Have a look at

http://homepage.ntlworld.com/g.knott/elect388.htm

OK, looked @ it, but I am wondering a bit as to why you thought _I_
should, (since nothing new shoved up) ?

(By the way, if you redraw the block schematic, nobody can accuse you of
theft of copyrighted material





--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *

 

[John Albers]

Soeren <Look@iNO-SPAMt.dk.invalid> wrote in message news:<Xns94D9C6C051984o8oLOOKatHOMEo8o@212.242.40.196>...

Hi John,


There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

Take a look at Tonys 555-tutor:
URL:http://www.uoguelph.ca/~antoon/gadgets/555/555.html

And/or (or should it be nand/nor get the datasheet for ICM7555 from
Philips (page 2 has a nice drawing which should help you).


However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters.

Actually, it is a drawing_error_gate

Thank You everyone for your input. I can see how the circuit works
when the top bubble is removed from the input of the OR gate.
However, during certain times in the cycle, bringing the RESET Pin (4)
low will result in a 1 on both inputs of the RS flip flop. This is a
bad thing, right?

 

[John Popelish]

John Albers wrote:

Soeren <Look@iNO-SPAMt.dk.invalid> wrote in message news:<Xns94D9C6C051984o8oLOOKatHOMEo8o@212.242.40.196>...
Hi John,


There is a really good graphical simulation of the inner worrkings of
a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.

Take a look at Tonys 555-tutor:
URL:http://www.uoguelph.ca/~antoon/gadgets/555/555.html

And/or (or should it be nand/nor get the datasheet for ICM7555 from
Philips (page 2 has a nice drawing which should help you).


However, I am trying to follow what is happening and think that I
almost understand. I need some clarification of what type of logic
gate is just before the Rst on the flip flop? It looks like an OR
gate and the two little circles just in front look like inverters.

Actually, it is a drawing_error_gate

Thank You everyone for your input. I can see how the circuit works
when the top bubble is removed from the input of the OR gate.
However, during certain times in the cycle, bringing the RESET Pin (4)
low will result in a 1 on both inputs of the RS flip flop. This is a
bad thing, right?

For any set reset flip flop and any given output, either set overrides
reset or reset overrides set if both are applied at the same time. In
the 555, reset overrides trigger (set) for both the output and the
discharge pin. If threshold goes high at the same time that trigger
is low, there is a battle between the collector current's of Q15 and
Q6 (on figure 4-2 of the above link, so it is not so clear which of
these wins the tug of war for the base voltage of Q16. It would be an
interesting experiment to see which wins.
--
John Popelish

 

[Soeren]

Hi John,

but from a
black box perspective, I think this is a functional description.
Please elaborate on how this model is wrong.

To reset the output of the 555, either the reset pin (4) must be
"low" *OR* the voltage on the threshold pin must be above 2/3 Vcc.

The "threshold comparator" output is "high" when the threshold pin
(6) is above 2/3 Vcc.

From this follows, that the NAND gate (OR w. inverted inputs) cannot
work, which is probably what confused John Albers.

Remove the topmost inverter-bubble on the OR gate and I will find
the description functional

The comparator shown for the threshold input is connected as
inverting, so that a high input will produce a low on the input of
the gate.

Inverting ? Like in "let's say plus is minus and v.v. without telling
anyone" ?

What on earth are you smoking, I want some

Please reread what I wrote and compare with
<URL:http://www.williamson-labs.com/480_555.htm>
(And please read the "+"sign as positive

And to repeat myself...
Remove the topmost inverter-bubble on the OR gate or it is wrong, bad,
defect, unusable, incorrect and pretty damn ugly ;-P

According to the approximate internal schematic shown on page 1 of:
http://www.national.com/ds/LM/LM555.pdf

We are discussing the williamson-labs drawing, not anything else (and
absolutely not a part of it out of context).

if you consider Q17 to be the output of the threshold comparator,
this comparator is connected to invert the polarity of the threshold
input. Its collector or Q17 is wire ORed (negative active ORed) with
the signal from the reset emitter follower to reset the flip flop
when either pulls low. So the model is usably accurate as far as I
can tell.

You cannot just compare a part of the circuit and expect the logic to
be correct.

Just take a _close_ look at the williamson-labs drawing, anybody with
just a hint of logic insight can tell the error - which is why the OP
wondered in the first place.

Do get some more sleep, if you cannot see it, I have much higher
thoughts about your abilities than what your postings in this thread
could lead to


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *

 

[Soeren]

Hi John,

However, during certain times in the cycle, bringing the RESET Pin
(4) low will result in a 1 on both inputs of the RS flip flop. This
is a bad thing, right?

Nope, it is build for it


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *