G
googler
Guest
This might sound like a naive question but please help me as I don't
have much experience using vcs. I am trying to use vcs to compile a
simple verilog code, run the simulation and view the waveform in
virsim. I run the entire thing as
$ vcs -RI counter.v
My testbench code looks as below (both the DUT and the testbench are
defined in counter.v).
module counter_tb();
// variable declarations
......
initial begin
$vcdpluson;
......
end
counter DUT(myclock, myrest, mycount);
.....
endmodule
The design compiles, virsim window comes up and I click on continue
which completes the simulation. I can see the correct results getting
printed by $display. After this, I open a hierarchy window and it shows
the testbench module counter_tb and the signals declared in the module.
(However, it does not show the DUT or any signal inside DUT. Why?) Now
when I try to view the waveform by opening up a waveform window and
then drag-drop (using left mouse button in my laptop) the signals in
counter_tb, nothing happens and I can't see any waveform. BTW, the file
vcdplus.vpd is created.
Please let me know what's wrong. Perhaps I am missing some options on
vcs command-line? Do I need to put $vcdpluson in my code to generate
the waveform? Or will it work even without $vcdpluson?
Also, if I want to generate the waveform info in fsdb format, then what
option shall I use for vcs command and what system call (corresponding
to $vcdpluson) is needed?
Thanks in advance.
have much experience using vcs. I am trying to use vcs to compile a
simple verilog code, run the simulation and view the waveform in
virsim. I run the entire thing as
$ vcs -RI counter.v
My testbench code looks as below (both the DUT and the testbench are
defined in counter.v).
module counter_tb();
// variable declarations
......
initial begin
$vcdpluson;
......
end
counter DUT(myclock, myrest, mycount);
.....
endmodule
The design compiles, virsim window comes up and I click on continue
which completes the simulation. I can see the correct results getting
printed by $display. After this, I open a hierarchy window and it shows
the testbench module counter_tb and the signals declared in the module.
(However, it does not show the DUT or any signal inside DUT. Why?) Now
when I try to view the waveform by opening up a waveform window and
then drag-drop (using left mouse button in my laptop) the signals in
counter_tb, nothing happens and I can't see any waveform. BTW, the file
vcdplus.vpd is created.
Please let me know what's wrong. Perhaps I am missing some options on
vcs command-line? Do I need to put $vcdpluson in my code to generate
the waveform? Or will it work even without $vcdpluson?
Also, if I want to generate the waveform info in fsdb format, then what
option shall I use for vcs command and what system call (corresponding
to $vcdpluson) is needed?
Thanks in advance.