I
Iris
Guest
Hi all,
I simulate verilog code using NC-verilog.
From the Schematic Editor > Launch > Simulation > NC-Verilog I run Verilog Environment. When I click Commands -> Initialize Design, the error happens. Follow the online tutorial, I find that I need to change "NC-Verilog Executable" in Setup -> Simulation.
However, I did not find the "ncxlmode" file in ".../tools.lnx86/inca/bin" directory or ".../tools.lnx86/inca/bin/64bit". The version of Cadence which used is 6.1.5
Could you pls give me some advices or suggestions to solve this problem?
Thank you so much and Best regards,
Iris
I simulate verilog code using NC-verilog.
From the Schematic Editor > Launch > Simulation > NC-Verilog I run Verilog Environment. When I click Commands -> Initialize Design, the error happens. Follow the online tutorial, I find that I need to change "NC-Verilog Executable" in Setup -> Simulation.
However, I did not find the "ncxlmode" file in ".../tools.lnx86/inca/bin" directory or ".../tools.lnx86/inca/bin/64bit". The version of Cadence which used is 6.1.5
Could you pls give me some advices or suggestions to solve this problem?
Thank you so much and Best regards,
Iris