Guest
I got a piece of VHDL which I cannot compile it with ModelSim 6.0 SE,
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated."
As I have understand it is because the the function is used after it
was declaread, but before it was actually writen in the package. See
code:
package xyz_pkg is
....
subtype analog is std_logic_vector(PW-1 downto 0);
....
function to_analog (constant value : real) return analog;
function to_analog (constant value : integer) return analog;
....
constant VDDP : analog := to_analog(3.3);
constant VTH : analog := to_analog(1.3);
constant VDDH : analog := to_analog(5.0);
constant VSS : analog := to_analog(0.0);
constant GND : analog := to_analog(0.0);
end xyz_pkg;
package body xyz_pkg is
....
-- purpose: convert real to analog
function to_analog (constant value : real) return analog is
begin
return analog(to_signed(integer(value*(2.0**(PW-IP))), PW));
end to_analog;
-- purpose: convert integer to analog
function to_analog ( constant value : integer) return analog is
begin
return analog(to_signed(value, PW));
end to_analog;
.....
end xyz_pkg;
If there an option in ModelSim to allow such a programming, or do I
have to change it. It works under NCSim.
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated."
As I have understand it is because the the function is used after it
was declaread, but before it was actually writen in the package. See
code:
package xyz_pkg is
....
subtype analog is std_logic_vector(PW-1 downto 0);
....
function to_analog (constant value : real) return analog;
function to_analog (constant value : integer) return analog;
....
constant VDDP : analog := to_analog(3.3);
constant VTH : analog := to_analog(1.3);
constant VDDH : analog := to_analog(5.0);
constant VSS : analog := to_analog(0.0);
constant GND : analog := to_analog(0.0);
end xyz_pkg;
package body xyz_pkg is
....
-- purpose: convert real to analog
function to_analog (constant value : real) return analog is
begin
return analog(to_signed(integer(value*(2.0**(PW-IP))), PW));
end to_analog;
-- purpose: convert integer to analog
function to_analog ( constant value : integer) return analog is
begin
return analog(to_signed(value, PW));
end to_analog;
.....
end xyz_pkg;
If there an option in ModelSim to allow such a programming, or do I
have to change it. It works under NCSim.