Can you make a vector of vectors?

Is there any way to declare a vector that consists of vectors?
I mean, if I type "input[7:0] r;" then i get r[0], r[1], ...., r[7]
where each r[] is a scalar, right?
But is there any way to make each r[] a vector so that I get something
similar to two-dimensional array in C or Java?

 

On Apr 20, 6:56 am, xicl...@gmail.com wrote:

Is there any way to declare a vector that consists of vectors?
I mean, if I type "input[7:0] r;" then i get r[0], r[1], ...., r[7]
where each r[] is a scalar, right?
But is there any way to make each r[] a vector so that I get something
similar to two-dimensional array in C or Java?

You can declare an array of vectors. The syntax of that is

reg [7:0] r [0:15];

to declare an array of 8-bit vectors.

However, you cannot pass an array through a module port in Verilog.

SystemVerilog allows declaring multi-dimensional vectors, and also
allows passing entire arrays through ports.