Can you implement a pull-up resistor in VHDL?

[Dave Pollum]

On Dec 4, 8:48 am, jid...@hotmail.com wrote:

Hello,

I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
resistors with ISE; however, i would like to do this in VHDL so that i
can enable them during runtime. At first I thought these lines would
synthese, but I was wrong.

entity pullup is
port (inp_i :in std_logic;
outp_o : out std_logic);
end pullup;

architecture rtl of pullup is
signal s_inp_i : std_logic;
begin
s_inp_i <= 'H';
s_inp_i <= inp_i;
outp_o <= inp_i;
end rtl;

Any Idea how to do this?

Thanks;
JJ

I don't know how to implement pull-up/pull-down, but you can't assign
values to input port "inp_i".
-Dave Pollum

 

[Jan]

You cannot dynamically enable/disable pullups in xilinx devices.
You can instantiate a PULLUP/PULLDOWN primitive, but it cannot change
after configuration..
see http://toolbox.xilinx.com/docsan/xilinx9/books/docs/s3edl/s3edl.pdf

 

[Peter]

Any Idea how to do this?

Hi,

I am not familiar with Xilinx software, but when designing with e.g.
Actel you instantiate a certain I/O-pad in your vhdl code.

/Peter

 

Hello,

I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
resistors with ISE; however, i would like to do this in VHDL so that i
can enable them during runtime. At first I thought these lines would
synthese, but I was wrong.


entity pullup is
port (inp_i :in std_logic;
outp_o : out std_logic);
end pullup;

architecture rtl of pullup is
signal s_inp_i : std_logic;
begin
s_inp_i <= 'H';
s_inp_i <= inp_i;
outp_o <= inp_i;
end rtl;

Any Idea how to do this?

Thanks;
JJ