Can you have multiple architecture declarations tied to the

A

Aldorus

Guest
newbie here ...

I have the following circuit (that will help me learn VHDL)
4 x seven segment displays to be controlled by one cpld. each of the
seven segment displays will decode a separate 3 bit register

I imagine the entity description should go like this:
entity ent_seven_seg_display is port (
itemstate: in bit_vector(2 downto 0);
sevseg : out bit_vector(6 downto 0));
end ent_seven_seg_display;

Is it possible to have 4 different architecture declarations all
referencing the above entity description

as in
architecture display1 of ent_seven_seg_display is
blah blah blah

architecture display2 of ent_seven_seg_display is
blah blah blah

architecture display3 of ent_seven_seg_display is
blah blah blah

architecture display4 of ent_seven_seg_display is
blah blah blah

?

Again bear in mind I have 4 seven segment displays that I want to decode
the state of 4 x 3 bit registers so at any given point in time each of
the seven segment displays will hold a different number.

I have one large CPLD with enough pins to handle this circuit ...

I just want to know if I can save having to create four entity
descriptions that are identical in everything BUT port names

Thanks
note to self: maybe I should finish reading this VHDL book before posing
such questions ...
 
Aldorus wrote:

Is it possible to have 4 different architecture declarations all
referencing the above entity description
Click to expand...
If I were feeling structural,
I could have four *instances* of the same
entity/architecture pair.

But I usually feel more like declaring
and array of registers in a single entity.

note to self: maybe I should finish reading this VHDL book before posing
such questions ...
Click to expand...
Good idea.
Another is to get a simulator and start with some working examples.

-- Mike Treseler
 
On 24 Apr., 00:03, Aldorus <h...@hereonearth.com> wrote:
newbie here ...

I have the following circuit (that will help me learn VHDL)
4 x seven segment displays to be controlled by one cpld. each of the
seven segment displays will decode a separate 3 bit register

I imagine the entity description should go like this:
entity ent_seven_seg_display is port (
       itemstate: in  bit_vector(2 downto 0);
       sevseg   : out bit_vector(6 downto 0));
end ent_seven_seg_display;

Is it possible to have 4 different architecture declarations all
referencing the above entity description

as in
architecture display1 of ent_seven_seg_display is
blah blah blah

architecture display2 of ent_seven_seg_display is
blah blah blah

architecture display3 of ent_seven_seg_display is
blah blah blah

architecture display4 of ent_seven_seg_display is
blah blah blah

?

Again bear in mind I have 4 seven segment displays that I want to decode
the state of 4 x 3 bit registers so at any given point in time each of
the seven segment displays will hold a different number.

I have one large CPLD with enough pins to handle this circuit ...

I just want to know if I can save having to create four entity
descriptions that are identical in everything BUT port names

Thanks
note to self: maybe I should finish reading this VHDL book before posing
such questions ...
Click to expand...
Hi Aldorus,
you are contradicting yourself in your posting. If you are using a
common entity all your architectures have to use te same port names.
But still you are free to write independent entities with the same
port names too.
Or did you mean: ...identical in everything BUT _Entity_ names... ?

anyway...

about VHDL:
Yo can use in line instantiation like this:

decoder1: entity work.decoder(arch1)
port map ...
decoder2: entity work.decoder(arch2)
port map ...

This works at least for simulation, you have to try it for synthesis.
Maybe not all tools can handle it.

about your design:
Looks like you need four 7-segment decoders.
I wonder why they should be different in any way?
In VHDL you are able to instantiate the same ent-arc pair multiple
times, and connect them do tifferent signals (keyword: structural
design). You will need a toplevel design anyway.
eg.:
decoder1: entity work.decoder(behavioral)
port map (itemstate => stateinput1,
sevseg => display1);
decoder2: entity work.decoder(behavioral)
port map (itemstate => stateinput2,
sevseg => display2);

Have a nice synthesis
Eilert
 
On 23 Apr, 23:03, Aldorus <h...@hereonearth.com> wrote:
newbie here ...

I have the following circuit (that will help me learn VHDL)
4 x seven segment displays to be controlled by one cpld. each of the
seven segment displays will decode a separate 3 bit register

I imagine the entity description should go like this:
entity ent_seven_seg_display is port (
       itemstate: in  bit_vector(2 downto 0);
       sevseg   : out bit_vector(6 downto 0));
end ent_seven_seg_display;

Is it possible to have 4 different architecture declarations all
referencing the above entity description

as in
architecture display1 of ent_seven_seg_display is
blah blah blah

architecture display2 of ent_seven_seg_display is
blah blah blah

architecture display3 of ent_seven_seg_display is
blah blah blah

architecture display4 of ent_seven_seg_display is
blah blah blah

?

Again bear in mind I have 4 seven segment displays that I want to decode
the state of 4 x 3 bit registers so at any given point in time each of
the seven segment displays will hold a different number.

I have one large CPLD with enough pins to handle this circuit ...

I just want to know if I can save having to create four entity
descriptions that are identical in everything BUT port names

Thanks
note to self: maybe I should finish reading this VHDL book before posing
such questions ...
Click to expand...
The only time I have seen multiple architectures for the same entity
is when there is a different architecture for simulation and synthesis
(normally to speed up simulation).

For the 7-seg display normally the decode would be the same, so why
cant you just instatiate the same entity 4 times connected to the 4
different registers?
 
On Thu, 23 Apr 2009 23:07:31 -0700, goouse wrote:

decoder1: entity work.decoder(behavioral)
port map (itemstate => stateinput1,
sevseg => display1);
decoder2: entity work.decoder(behavioral)
port map (itemstate => stateinput2,
sevseg => display2);

Have a nice synthesis
Eilert
Click to expand...
Thanks this was very helpful
 
Hi Aldorus,
Before you start writing the VHDL code, make sure you draw
a picture (block diagram) of what you want. Often with seven
segment displays are connected with a common anode or
common cathode connection. This would mean that only one
display value can be driven at a time and you can take
advantage of this.

If you find you have 4 entirely separately controlled
segments (such as the Altera/Terasic DE1 has),
having 4 instances of a single entity that controls a
single segment is fine (as described in other threads).

OTOH, if you have a common anode connection (such as the
Digilent Basys and Nexsys boards have), then somewhere
you will have to multiplex the separate values onto the
cathode lines. While the same approach used previously will
work, it creates more hardware than you need. You will
have 4 copies of the decode logic. Instead, you can
multiplex your registers first then only have one copy
of the decode logic.

In summary:
+ read your VHDL text or at least a tutorial such as:
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html

+ Before coding, draw a picture of what hardware you want.
+ Before writing code, write comments in the file that reflect
what is in the block diagram
+ Write code

Good luck. Trying to code without reading the book can be
both frustrating and time consuming.

Cheers,
Jim
SynthWorks VHDL Training
 
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