Can XILINX run in multiple instances?

[Patrick Browne]

Hi everyone,
I am working on a project and I need to run different designs on a
variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs
running at once. I noticed that XILINX will not run in multiple
instances. Is there any way that I can (1) simulate such a system? (2)
download the design for each FPGA to that particular FPGA?

- Thanks in advance.

 

[Brannon King]

I have a board with ten Virtex2 chips on it and they all run at the same
time. I don't ever do simulations of the whole thing together, though. I
simulate the parts, put them together, put them into the chips, and then
pray she works. Most of the issues I've had have been with wire termination
between chips and clock signal synchronization, and I don't know that you
can simulate those very well anyhow. The bus controller on my board handles
the programming of each of the chips through SelectMap Slave mode, though
when I was working on the bus controller I could program all the chips with
the JTAG.

"Patrick Browne" <pbrowne0@excite.com> wrote in message
news:15e7d80c.0401160839.2cd76ec9@posting.google.com...

Hi everyone,
I am working on a project and I need to run different designs on a
variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs
running at once. I noticed that XILINX will not run in multiple
instances. Is there any way that I can (1) simulate such a system? (2)
download the design for each FPGA to that particular FPGA?

- Thanks in advance.

 

[Hal Murray]

I am working on a project and I need to run different designs on a
variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs
running at once. I noticed that XILINX will not run in multiple
instances.

What does that mean? How does a chip know wheather it is running
alone or is part of a clump?

Is there any way that I can (1) simulate such a system? (2)
download the design for each FPGA to that particular FPGA?

[I'm not a simulation wizard. No comments there.]

Each chip has a set of pins that you use to load it. If you
connect those pins up to the right source of bits you get the
right design loaded into your chip.

I suggest reading the data sheet. There is a big section on
configuration. It's all there, but may take several passes to
understand it.

It's common to share many of the configuration pins by connecting
several chips in a daisy chain. For two chips, you need to feed
them twice as many bits - roughly one set of bits for each chip.

You can load the same program into several chips if that's what
you want to do. In that case, you only need one copy of the
bits, but you have to wire up the chips differently than the
daisy chain - parallel rather than series.

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[Bob Perlman]

On 16 Jan 2004 08:39:37 -0800, pbrowne0@excite.com (Patrick Browne)
wrote:

I noticed that XILINX will not run in multiple instances.

What does this mean?

Bob Perlman
Cambrian Design Works

 

[Mike Treseler]

Patrick Browne wrote:

I would like to have 4 to 9 FPGAs running at once.

Consider designing the system using an HDL with
a separate entity/module for each FPGA.

For functional simulation you may instance as many
entities as you like into a single testbench.

I noticed that XILINX will not run in multiple
instances.

Wait until your functional simulation work is complete
before you attempt synthesis. With a properly
synchronized design, code and netlist sims
should work the same.


-- Mike Treseler

 

[Patrick Browne]

Thanks for responding. What I mean is that I have 9 designs, each
desined for a different chip, but each chip must interact with the
others. Therefore, to simulate this environment I need to run an
implementation and simulation for each chip and have the outputs of
the chips interacting with one another. Since XILINX's Project Manager
only loads one chip's design at a time, I would need to have many
instances of it running at once and to have them interact with one
another. It is a real time system so the response time, and
communication between chips are crucial.

I really appreciate Mike Treseler's suggestion to represent each chip
as an HDL module and then simulate the design. My main concern with
this though is whether I could get a target FPGA with enough space for
the nine designs. Also, I noted that Brandon King has a system with
similar complexity as mine. I don't have my board built as yet and was
wondering if there is any place I can ask to build a board for me with
9 Virtex FPGAs.

Thanks so much for the responses.

Bob Perlman <bobsrefusebin@hotmail.com> wrote in message news:<c51k00lpi09inh4kb69ogettgmgrc4dpkn@4ax.com>...

On 16 Jan 2004 08:39:37 -0800, pbrowne0@excite.com (Patrick Browne)
wrote:

I noticed that XILINX will not run in multiple instances.

What does this mean?

Bob Perlman
Cambrian Design Works

 

[Bob Perlman]

On 19 Jan 2004 10:55:15 -0800, pbrowne0@excite.com (Patrick Browne)
wrote:

Thanks for responding. What I mean is that I have 9 designs, each
desined for a different chip, but each chip must interact with the
others. Therefore, to simulate this environment I need to run an
implementation and simulation for each chip and have the outputs of
the chips interacting with one another. Since XILINX's Project Manager
only loads one chip's design at a time, I would need to have many
instances of it running at once and to have them interact with one
another. It is a real time system so the response time, and
communication between chips are crucial.

Do you want to:

1) simulate the FPGAs on a computer

2) emulate the desired functions in actual hardware

3) both?

For (1), you can use virtually any HDL simulator. As Mike suggested,
you have a (top-level) module for each FPGA, and another top-level
module that ties them all together.

For (2), you build a board with multiple FPGAs, or buy a board; the
Dini Group makes stuff like this.

I'm not sure what any of this has to do with Xilinx Project Manager.

Bob Perlman
Cambrian Design Works

 

[Patrick Browne]

Thanks Bob. Actually I need to do both. However, right now I'm at the
simulation stage. I'm writing a program in C that will automatically
implement changes to a particular design involving 9 FPGAs. So it has
to call the XILINX tools and coordinate the operation and debugging of
the system.

I had asked a few companies to do a board with 9 FPGAs for me but few
responded positively and the only estimate I got costs 50000 euros.
This was a bit over my budget so I decided not to try the
implementation as yet. But If I can get such a board I would add the
implementation to my objectives.

Bob Perlman <bobsrefusebin@hotmail.com> wrote in message news:<pnao001vajgongu23hui0qmgdhv41jof7b@4ax.com>...

On 19 Jan 2004 10:55:15 -0800, pbrowne0@excite.com (Patrick Browne)
wrote:

Thanks for responding. What I mean is that I have 9 designs, each
desined for a different chip, but each chip must interact with the
others. Therefore, to simulate this environment I need to run an
implementation and simulation for each chip and have the outputs of
the chips interacting with one another. Since XILINX's Project Manager
only loads one chip's design at a time, I would need to have many
instances of it running at once and to have them interact with one
another. It is a real time system so the response time, and
communication between chips are crucial.

Do you want to:

1) simulate the FPGAs on a computer

2) emulate the desired functions in actual hardware

3) both?

For (1), you can use virtually any HDL simulator. As Mike suggested,
you have a (top-level) module for each FPGA, and another top-level
module that ties them all together.

For (2), you build a board with multiple FPGAs, or buy a board; the
Dini Group makes stuff like this.

I'm not sure what any of this has to do with Xilinx Project Manager.

Bob Perlman
Cambrian Design Works

 

[Philip Freidin]

On 19 Jan 2004 10:55:15 -0800, pbrowne0@excite.com (Patrick Browne) wrote:

Thanks for responding. What I mean is that I have 9 designs, each
desined for a different chip, but each chip must interact with the
others.

So a board with 9 FPGAs, each with a different design. The chips
communicate with each other.

Therefore, to simulate this environment I need to run an
implementation and simulation for each chip and have the outputs of
the chips interacting with one another.

No you don't need to run implementation to run simulation. You can
(and should) run a pre place and route simulation. These
also simulate faster than the post P&R simulations, but they
do not contain timing information. This is also sometimes called
unit-delay or functional simulation. If you have been a good boy
and done fully synchronous design, these simulations can be
sufficient for robust design, and the timing simulation (must be
post P&R) is not needed.

If you create a test bench for each design, you can test each design
in isolation. In a multi chip design like yours, this may not be the
best plan, as the interactions may be hard to describe in a test
bench.

Since XILINX's Project Manager only loads one chip's design at a time,
I would need to have many instances of it running at once and to have
them interact with one another.

No you don't. The Xilinx project manager is just a shell that runs
separate programs. The simulation program (which I am guessing is
Modelsim) can be run outside the Xilinx project manager. In fact you
can probably find out how the project manager starts up modelsim,
then just do it for your self. This will be somewhat less circuitous
and will use less memory on your PC, as there is no actual need for
the Xilinx project manager to be running when you are running your
simulation. So this is how you run one designs simulation.

You can run a multichip simulation the same way, and you only need
one instance of the simulator running. Here's how:

Let's say your 9 designs are named PB1 through PB9. Each has a top
level, and the I/O of the top level is the pins that will be on the
FPGA. Each of your designs probably has a different I/O list.

You now create a system simulation test bench that is hierarchically
one level higher than your 9 designs. In fact it represents your board.
In this file you instantiate one of each of your designs PB1 .. PB9,
and you connect between their I/O just as you expect your board to be
wired. And I/O that are left over (i.e. not going between the FPGAs)
are your system level in's and out's. Your test bench must drive
these inputs with appropriate test signals and the outputs are probably
what you care about.

As you can see, there is no need to be running the Xilinx project manager,
nor is there a need to push the 9 designs through P&R to do this.
This is all unit-delay, pre P&R simulation.

It is a real time system so the response time, and
communication between chips are crucial.

I really appreciate Mike Treseler's suggestion to represent each chip
as an HDL module and then simulate the design. My main concern with
this though is whether I could get a target FPGA with enough space for
the nine designs.

I hope you now understand that there is no need for such a huge FPGA,
since you do not have to get all into 1 FPGA to do this simulation.

Also, I noted that Brandon King has a system with
similar complexity as mine. I don't have my board built as yet and was
wondering if there is any place I can ask to build a board for me with
9 Virtex FPGAs.

There are many companies that will build boards, but this is not going
to be cheap. You may want to look at products from the Dini group
that specifically makes such boards: http://www.dinigroup.com/

Or another company to look at is Aptix.

Either way, sit down before you ask the price. Even though the prices
will seem high, they will be cheaper than trying to do it your self.




Philip Freidin
Fliptronics