can we have a portless module to define header files in veri

[shwetika]

Can we have a file called “abc.v” analogous to “abc.h” in C and
include it in a portless abc module used only to include this file so
that we could have a syntax similar to Java (y=abc.somefunction(x))
and allow the code to be shared by several modules...e.g. y=abc.sin(x)

Thanks
Shwetika

 

On Jun 11, 3:56 pm, shwetika <shwetikaku...@gmail.com> wrote:

Can we have a file called “abc.v” analogous to “abc.h” in C and
include it in a portless abc module used only to include this file so
that we could have a syntax similar to Java (y=abc.somefunction(x))
and allow the code to be shared by several modules...e.g. y=abc.sin(x)

Yes, this approach is sometimes used in Verilog for "libraries" of
utility functions. It is made even easier to use by the fact that
Verilog will treat unresolved function names as hierarchical
references and do an upward search for them.

In SystemVerilog, you would use a package instead.

 

[shwetika]

On Jun 12, 4:18 pm, sh...@cadence.com wrote:

On Jun 11, 3:56 pm, shwetika <shwetikaku...@gmail.com> wrote:

Can we have a file called “abc.v” analogous to “abc.h” in C and
include it in a portless abc module used only to include this file so
that we could have a syntax similar to Java (y=abc.somefunction(x))
and allow the code to be shared by several modules...e.g. y=abc.sin(x)

Yes, this approach is sometimes used in Verilog for "libraries" of
utility functions. It is made even easier to use by the fact that
Verilog will treat unresolved function names as hierarchical
references and do an upward search for them.

In SystemVerilog, you would use a package instead.

I was wondering..how would i be able to synthesize the portless
module.Does it even need to pass the synthesis stage?if not then where
should this module be stored/saved and how do i include it in other
modules to be able to use the java syntax.
Thanks
shwetika

 

On Jun 12, 4:24 pm, shwetika <shwetikaku...@gmail.com> wrote:

I was wondering..how would i be able to synthesize the portless
module.Does it even need to pass the synthesis stage?if not then where
should this module be stored/saved and how do i include it in other
modules to be able to use the java syntax.

Synthesis tools generally reject hierarchical names, so you might not
be able to use this approach for synthesizable code. Instead, you
would probably have to include a copy of the function locally to each
module that wanted to use it.