can u say watz wrong in this program

[jammy]

module dec(a,b,d)
input a,b;
output d;
if(a==1'b0 && b==1'b0)
d=0001;
else if(a==1'b0 && b==1'b1)
d=0010 ;
else if(a==1'b1 && b==1'b0)
d=0100;
else(a==1'b1 && b==1'b1)
d=1000;
end module

module dec_test;
reg a,b;
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
dec d1(a,b,d);
initial $monitor($time,"a=%b,b=%b,output=%b",a,b,d);
initial #100 $finish;
endmodule

 

[mk]

On Mon, 30 Jul 2007 09:14:20 -0700, jammy <jaweth_r@yahoo.co.in>
wrote:

module dec(a,b,d)
input a,b;
output d;
if(a==1'b0 && b==1'b0)
d=0001;

d is declared incorrectly.

 

[Mike Lewis]

"jammy" <jaweth_r@yahoo.co.in> wrote in message
news:1185812060.373592.281270@e9g2000prf.googlegroups.com...

module dec(a,b,d)
input a,b;
output d;
if(a==1'b0 && b==1'b0)
d=0001;
else if(a==1'b0 && b==1'b1)
d=0010 ;
else if(a==1'b1 && b==1'b0)
d=0100;
else(a==1'b1 && b==1'b1)
d=1000;
end module

module dec_test;
reg a,b;
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
dec d1(a,b,d);
initial $monitor($time,"a=%b,b=%b,output=%b",a,b,d);
initial #100 $finish;
endmodule

well ..
1. you didn't define d as a reg
2. you don't have an always block around your code
3. would look much nicer if it was done as a case
4. your missing some semi-colons


ok ... I'm on lunch .. here is how I would code up dec

module dec(a,b,d);
input a,b;
output d;

reg d;

always @ (*)
begin
case ({b,a})
2'h0 : d = 4'h0000;
2'h1 : d = 4'h0010;
2'h2 : d = 4'h0100;
2'h3 : d = 4'h1000;
endcase
end
end module

 

[mjl296@hotmail.com]

On 30 Jul, 17:33, "Mike Lewis" <some...@micrsoft.com> wrote:

"jammy" <jawet...@yahoo.co.in> wrote in message

news:1185812060.373592.281270@e9g2000prf.googlegroups.com...



module dec(a,b,d)
input a,b;
output d;
if(a==1'b0 && b==1'b0)
d=0001;
else if(a==1'b0 && b==1'b1)
d=0010 ;
else if(a==1'b1 && b==1'b0)
d=0100;
else(a==1'b1 && b==1'b1)
d=1000;
end module

module dec_test;
reg a,b;
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
dec d1(a,b,d);
initial $monitor($time,"a=%b,b=%b,output=%b",a,b,d);
initial #100 $finish;
endmodule

well ..
1. you didn't define d as a reg
2. you don't have an always block around your code
3. would look much nicer if it was done as a case
4. your missing some semi-colons

ok ... I'm on lunch .. here is how I would code up dec

module dec(a,b,d);
input a,b;
output d;

reg d;

always @ (*)
begin
case ({b,a})
2'h0 : d = 4'h0000;
2'h1 : d = 4'h0010;
2'h2 : d = 4'h0100;
2'h3 : d = 4'h1000;
endcase
end
end module

output [3:0] d;
reg [3:0] d;

 

[Mike Lewis]

<mjl296@hotmail.com> wrote in message
news:1185869267.014338.301350@g12g2000prg.googlegroups.com...

On 30 Jul, 17:33, "Mike Lewis" <some...@micrsoft.com> wrote:
"jammy" <jawet...@yahoo.co.in> wrote in message

news:1185812060.373592.281270@e9g2000prf.googlegroups.com...



module dec(a,b,d)
input a,b;
output d;
if(a==1'b0 && b==1'b0)
d=0001;
else if(a==1'b0 && b==1'b1)
d=0010 ;
else if(a==1'b1 && b==1'b0)
d=0100;
else(a==1'b1 && b==1'b1)
d=1000;
end module

module dec_test;
reg a,b;
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
dec d1(a,b,d);
initial $monitor($time,"a=%b,b=%b,output=%b",a,b,d);
initial #100 $finish;
endmodule

well ..
1. you didn't define d as a reg
2. you don't have an always block around your code
3. would look much nicer if it was done as a case
4. your missing some semi-colons

ok ... I'm on lunch .. here is how I would code up dec

module dec(a,b,d);
input a,b;
output d;

reg d;

always @ (*)
begin
case ({b,a})
2'h0 : d = 4'h0000;
2'h1 : d = 4'h0010;
2'h2 : d = 4'h0100;
2'h3 : d = 4'h1000;
endcase
end
end module


output [3:0] d;
reg [3:0] d;

you got me ... that's why there is simulation (which I didn't exercise).

Mike