can there be nested named blocks in verilog

[parag_paul@hotmail.com]

hi all,
I am trying to do something like the following


initial begin : p1
reg a;
begin:
reg a;
end
end


Is the above possible

 

[Mike Treseler]

parag_paul@hotmail.com wrote:

hi all,
I am trying to do something like the following


initial begin : p1
reg a;
begin:
reg a;
end
end


Is the above possible

Yes, you have to name the block.
(I like to name mine "process"

always @(posedge clock or posedge reset)
begin: process // named block
// register_v declarations
...

For details see:
http://home.comcast.net/~mike_treseler/count_enable.v


-- Mike Treseler

 

On Jan 7, 8:07 am, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:

hi all,
I am trying to do something like the following

initial begin : p1
reg a;
begin:
reg a;
end
end

Is the above possible

You left out the name of the inner block, but aside from that it is
possible.

 

[Dwayne Dilbeck]

Yes, nesting named blocks in verilog is possible. The others have given you
good pointers. I would go further and say name all your blocks. It will
save you headaches when you start dealing with "generate" statements .
Different tools will deal with unnamed blocks in "generate" statements
differently. Sometimes even differently between each of the tools available
from a company. Making out of model references(OOMR) difficult. Granted I
suggest not using OOMRs, but they are useful in the Testbench and
assertions.

<parag_paul@hotmail.com> wrote in message
news:26d1c6dc-bff9-4934-80ce-b5e5750454d1@e10g2000prf.googlegroups.com...

hi all,
I am trying to do something like the following


initial begin : p1
reg a;
begin:
reg a;
end
end


Is the above possible

 

Dwayne Dilbeck wrote:

I would go further and say name all your blocks. It will
save you headaches when you start dealing with "generate" statements .
Different tools will deal with unnamed blocks in "generate" statements
differently. Sometimes even differently between each of the tools available
from a company. Making out of model references(OOMR) difficult. Granted I
suggest not using OOMRs, but they are useful in the Testbench and
assertions.

The IEEE Std 1364-2005 specifies an algorithm for creating a
standardized compiler-generated name for "unnamed" generate blocks.
So compliant tools should get the same results.

The standard also says it is illegal to use such compiler-generated
names in hierarchical references (OOMRs) inside the design.
Modifications to the design could change the generated names too
easily, so this rule protects you against writing such "brittle" code.

If you want to refer to something inside one of these blocks from
outside, you have to follow Dwayne's advice and name them yourself.