Can the Generate statement be compiled by iverilog?

[kb33]

Is the generate statement supported by the latest snapshot? I seem to
be running into problems compiling it.

kb33

 

[Stephen Williams]

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kb33 wrote:

Is the generate statement supported by the latest snapshot? I seem to
be running into problems compiling it.

Yes, all kinds.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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[kb33]

On Mar 26, 3:45 pm, Stephen Williams <spamt...@icarus.com> wrote:

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kb33 wrote:
Is the generate statement supported by the latest snapshot? I seem to
be running into problems compiling it.

Yes, all kinds.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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Thanks for the info. However, I was wondering if it is legal to use
two or more generate_loop_statements in a generate block, something
like the following:

genvar i,j;

generate
for (i=0; i<`LIMIT; i=i+1) begin:loop_1

 

[kb33]

On Mar 26, 3:45 pm, Stephen Williams <spamt...@icarus.com> wrote:

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Hash: SHA1

kb33 wrote:
Is the generate statement supported by the latest snapshot? I seem to
be running into problems compiling it.

Yes, all kinds.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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Thanks for the info. Can somebody let me know if having 2 or more
generate_loop_statements in a single generate block are legal? Like:

genvar i,j;

generate
for (i=0; i<`LIMIT_1; i=i+1)
begin: loop_1
.........
end

for (j=0; j<`LIMIT_2; j=j+1)
begin: loop_2
........
end

.....and so on....

endgenerate

I do not seem to be getting any error compiling or synthesizing this
type of code, but just wanted to make sure it is correct.

kb33

 

On Mar 26, 7:21 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Can somebody let me know if having 2 or more
generate_loop_statements in a single generate block are legal? Like:

Yes.

In fact the generate..endgenerate keywords are optional in
Verilog-2005.