Can primetime work without constraints?

[Fazela]

Hi Group,
I am a new user of Synopsys Primetime. I have a verilog design, on
which timing analysis is to be done. Now I am not aware of the maximum
register to register delay and so I do not understand as to what kind
of clock constraint should I apply. Can primetime analyse the design
and use a default clock or such if I dont give it one.

Thanks,
Fazela

 

[michaelst@gmail.com]

What do you want to "analyze" without clock?

 

[Fazela]

Hi Michael,

Its a basic counter design. And I want Primetime to generate all the
critical paths (and if possible all the paths of the circuit) But I
dont know what clock to use.

Thanks,
Fazela

 

[Fazela]

Hi Michael,

Its a basic counter design. And I want Primetime to generate all the
critical paths (and if possible all the paths of the circuit) But I
dont know what clock to use.

Thanks,
Fazela

 

[michaelst@gmail.com]

Critical path for what? You must define at least one constraint and
than use report_timing command.

 

[ABC]

Hi Fazela,
Try to assign a default clock period through derive_clock command where
it will automatically generate create clock command to all the primary
input clock ports and do a report timing to identify the reg to reg
critical paths.

Best regards,
ABC