F
Fazela
Guest
Hi Group,
I am a new user of Synopsys Primetime. I have a verilog design, on
which timing analysis is to be done. Now I am not aware of the maximum
register to register delay and so I do not understand as to what kind
of clock constraint should I apply. Can primetime analyse the design
and use a default clock or such if I dont give it one.
Thanks,
Fazela
I am a new user of Synopsys Primetime. I have a verilog design, on
which timing analysis is to be done. Now I am not aware of the maximum
register to register delay and so I do not understand as to what kind
of clock constraint should I apply. Can primetime analyse the design
and use a default clock or such if I dont give it one.
Thanks,
Fazela