Can port Maps be expressions?

[Shannon]

Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
sload => lockout_sload,
q => lockout_cnt
);

Shannon

 

[Alan Fitch]

Shannon wrote:

Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
sload => lockout_sload,
q => lockout_cnt
);

Shannon

No, not currently

Alan

P.S. The feature is introduced in VHDL2008 which should be standardised
by the IEEE this year.

--
Alan Fitch
Doulos
http://www.doulos.com

 

[Brian Drummond]

On Wed, 24 Sep 2008 08:58:26 -0700 (PDT), Shannon <sgomes@sbcglobal.net>
wrote:

Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
This one is not allowed in current VHDL.
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
This (type conversion) is legal, but there is at least one simulator

(Brand X) that fails if the port is in an entity instantiation, though
strangely enough it works in a component instantiation.

- Brian

 

[Shannon]

On Sep 24, 9:08 am, Alan Fitch <alan.fi...@spamtrap.com> wrote:

Shannon wrote:
Does VHDL allow expressions in port maps?  For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
   PORT MAP(
   clock           => MClk,
   cnt_en          => lockout_cnt_en AND NOT lockout_eq0,
   data            => STD_LOGIC_VECTOR(LOCKOUT_TIME),
   sload           => lockout_sload,
   q               => lockout_cnt
   );

Shannon

No, not currently

Alan

P.S. The feature is introduced in VHDL2008 which should be standardised
by the IEEE this year.

--
Alan Fitch
Douloshttp://www.doulos.com

Thank you.

 

[Alan Fitch]

Brian Drummond wrote:

On Wed, 24 Sep 2008 08:58:26 -0700 (PDT), Shannon <sgomes@sbcglobal.net
wrote:

Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
This one is not allowed in current VHDL.
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
This (type conversion) is legal, but there is at least one simulator
(Brand X) that fails if the port is in an entity instantiation, though
strangely enough it works in a component instantiation.

- Brian

Well spotted Brian, I didn't notice the array type conversion. Yes type
conversions are allowed. Array type conversions were not allowed in VHDL
87, but are allowed from VHDL 93 onwards.

Other type conversions may be implemented as functions, but the rule is
that the function may only have one argument,

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com

 

[Andy]

On Sep 25, 3:48 am, Alan Fitch <alan.fi...@spamtrap.com> wrote:

The "type conversion" need not be just a type conversion. It must be a
function with exactly one argument, and the return type of the
function must be constrained.

For example, invert(lockout_time) would also work, if invert() returns
a constrained type. The data type need not actually change.

The same restriction applies to a type conversion, unless it is an
implicit conversion (e.g. from numeric_std.unsigned to SLV).

I saw a paper several years ago that used conversion functions in
configuration port maps to allow substitution of integer vs vector
based models.

Andy