B
bigyellow
Guest
Is it possible?
Navigation
Install the app
How to install the app on iOS
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
More options
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an alternative browser.
You should upgrade or use an alternative browser.
H
HT-Lab
Guest
"bigyellow" <bigyellow@gmail.com> wrote in message
news:ac367673-4a35-44b1-9597-5fd299e4d574@t54g2000hsg.googlegroups.com...
Hans
www.ht-lab.com
news:ac367673-4a35-44b1-9597-5fd299e4d574@t54g2000hsg.googlegroups.com...
yes.Is it possible?
Hans
www.ht-lab.com
J
Jonathan Bromley
Guest
On Mon, 30 Jun 2008 07:22:40 -0700 (PDT), bigyellow wrote:
answer is plainly "yes, if you have SystemVerilog assertions
support in your tools".
For VHDL there is no LRM-defined mechanism, but....
1) Any tool that supports mixed-language VHDL/SystemVerilog
simulation (and that means all the big players, provided
you buy sufficiently powerful versions of the tool and get
all the necessary licences) would allow you to create a
module with a load of SV assertions in it, and connect that
module to signals in a VHDL design.
2) SystemVerilog has a construct called "bind" which allows
you to connect any SystemVerilog module at any point in
your design hierarchy. This is a great way to introduce
any passive monitoring block (i.e. a module with only input
ports, no outputs or inouts) into some existing design where
you don't want to disturb the source code. And "bind" is so
cool that the vendors also have done the necessary work
so that this binding works across VHDL/SV langauge boundaries.
Again you will need fairly up-market versions of the tools,
with the necessary licence features enabled - ask your local
apps engineer for the details.
3) There may be other tool-defined mechanisms for integrating
SVA with other languages. Again, ask your tool vendor.
So the quick answer is "yes, but it may cost".
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Verilog is a subset of SystemVerilog, so in that case theIs it possible?
answer is plainly "yes, if you have SystemVerilog assertions
support in your tools".
For VHDL there is no LRM-defined mechanism, but....
1) Any tool that supports mixed-language VHDL/SystemVerilog
simulation (and that means all the big players, provided
you buy sufficiently powerful versions of the tool and get
all the necessary licences) would allow you to create a
module with a load of SV assertions in it, and connect that
module to signals in a VHDL design.
2) SystemVerilog has a construct called "bind" which allows
you to connect any SystemVerilog module at any point in
your design hierarchy. This is a great way to introduce
any passive monitoring block (i.e. a module with only input
ports, no outputs or inouts) into some existing design where
you don't want to disturb the source code. And "bind" is so
cool that the vendors also have done the necessary work
so that this binding works across VHDL/SV langauge boundaries.
Again you will need fairly up-market versions of the tools,
with the necessary licence features enabled - ask your local
apps engineer for the details.
3) There may be other tool-defined mechanisms for integrating
SVA with other languages. Again, ask your tool vendor.
So the quick answer is "yes, but it may cost".
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.