Can I use pullup/pulldown to bias LVDS input?

[Symon]

Dear All,
Problem.
I've just been let down by a oscillator manufacturer. They
can only make the ordered 3.3V differential LVPECL oscillator parts
work at 5V. Some excuse about their quartz supplier. So, I can't stick
5V PECL into my 3.3V Virtex-E differential input, it's outside the
common mode range. So, I could AC couple it with a couple of caps
after the PECL driver's emitter resistors. I then need to bias the
signal into the common mode range of the VirtexE diff input.
Question.
Anybody know if I could somehow activate the internal
pullup resistor on one input and the pulldown on the other to bias the
signal in the middle of the supply? There's already a 100 ohm
termination resistor between the pins. Or, any better ideas?
cheers all, Syms.

p.s. I know I could use more resistors to do this biasing, but the
board layout makes this awkward. The VirtexE is, of course, a BGA.

 

[Bob]

Symon,

The problem with using the pullup/pulldown idea (if it's even possible) is
that the values of the pullups and pulldowns are not tightly controlled. The
common-mode point would thus not be in the middle of your 3.3V supply.

What might work is:

If you're able to enable the pullups, then the intrinsic diodes of the IOB's
will keep the positive peaks of the signal clamped to one diode drop above
3.3V (assuming it's cap coupled from your source). The negative peaks should
be well below the 3.3V supply. Also, the diode current will be small.

You should check with Xilinx to see if this approach will work, because the
signal swing may not be within their diffamp's input range.

Bob


"Symon" <symon_brewer@hotmail.com> wrote in message
news:a28bc07f.0309261442.131ae253@posting.google.com...

Dear All,
Problem.
I've just been let down by a oscillator manufacturer. They
can only make the ordered 3.3V differential LVPECL oscillator parts
work at 5V. Some excuse about their quartz supplier. So, I can't stick
5V PECL into my 3.3V Virtex-E differential input, it's outside the
common mode range. So, I could AC couple it with a couple of caps
after the PECL driver's emitter resistors. I then need to bias the
signal into the common mode range of the VirtexE diff input.
Question.
Anybody know if I could somehow activate the internal
pullup resistor on one input and the pulldown on the other to bias the
signal in the middle of the supply? There's already a 100 ohm
termination resistor between the pins. Or, any better ideas?
cheers all, Syms.

p.s. I know I could use more resistors to do this biasing, but the
board layout makes this awkward. The VirtexE is, of course, a BGA.

 

[Symon]

Hi Bob,
Thanks for your reply! My thoughts were that the common mode
range of the diff amps is quite good so any mismatch in the resistor
values wouldn't matter too much. However, the spec range doesn't work
beyond the rails, so I didn't want to use the diodes to limit the
common mode swing.
I'm fairly sure that it's just the software that stops you
turning the pullup/pulldowns on in diff input mode, a shame because
this would be useful in AC coupled apps. (I'd turn on all four
resistors on the two input pins) I guess it could be a bummer to
charactarise so Xilinx won't support this. Maybe I'll raise a webcase.
thanks again mate, Syms.

"Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:<zqldb.6531$NX3.2641@newsread3.news.pas.earthlink.net>...

Symon,

The problem with using the pullup/pulldown idea (if it's even possible) is
that the values of the pullups and pulldowns are not tightly controlled. The
common-mode point would thus not be in the middle of your 3.3V supply.

What might work is:

If you're able to enable the pullups, then the intrinsic diodes of the IOB's
will keep the positive peaks of the signal clamped to one diode drop above
3.3V (assuming it's cap coupled from your source). The negative peaks should
be well below the 3.3V supply. Also, the diode current will be small.

You should check with Xilinx to see if this approach will work, because the
signal swing may not be within their diffamp's input range.

Bob


"Symon" <symon_brewer@hotmail.com> wrote in message
news:a28bc07f.0309261442.131ae253@posting.google.com...
Dear All,
Problem.
I've just been let down by a oscillator manufacturer. They
can only make the ordered 3.3V differential LVPECL oscillator parts
work at 5V. Some excuse about their quartz supplier. So, I can't stick
5V PECL into my 3.3V Virtex-E differential input, it's outside the
common mode range. So, I could AC couple it with a couple of caps
after the PECL driver's emitter resistors. I then need to bias the
signal into the common mode range of the VirtexE diff input.
Question.
Anybody know if I could somehow activate the internal
pullup resistor on one input and the pulldown on the other to bias the
signal in the middle of the supply? There's already a 100 ohm
termination resistor between the pins. Or, any better ideas?
cheers all, Syms.

p.s. I know I could use more resistors to do this biasing, but the
board layout makes this awkward. The VirtexE is, of course, a BGA.

 

[Peter Monta]

symon_brewer@hotmail.com (Symon) writes:

... So, I can't stick
5V PECL into my 3.3V Virtex-E differential input, it's outside the
common mode range. So, I could AC couple it with a couple of caps
after the PECL driver's emitter resistors.

How about just a DC-coupled resistive divider to ground, doubling
as the emitter load? A (3.3/5) ratio would put the common-mode
voltage about right, and 3 dB of attenuation is no big deal.